CORPORA TID

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1983

Components

Handbook

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Western Di'gital

1983 Components

Handbook

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Making The Leading Edge Work For You"

This handbook is designed for you, the design engineer. It's in·

tended to be a useful tool, to enable you to make a preliminary evaluation of our products and, later, with samples in hand, to design our products into your own systems.

The data in these pages have been reviewed by our Marketing, Engineering, Manufacturing and Quality groups. Now we would like you to review the information we've provided and tell us how we can improve it. Please feel free to suggest any changes, additions, or clarifications that occur to you. And don't hesitate to call to our attention any sins of omission or commission we may have made.

We're eager to help upgrade the quality of information our industry provides to its customers. So, please, help us. Direct your com·

ments to:

Director of Corporation Communications WESTERN DIGITAL CORPORATION 2445 McCabe Way

Irvine, CA 92714 (714) 557-3550

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Western Digital: Update '83

Western Digital is on the move, growing and expanding to meet your needs. This year's Components Handbook includes a number of significant new products. Our leadership in file management is reinforced by the many innovations this year in both floppy disk and Winchester disk controllers, and the introduction of the first LSI controller for SMD drives. We've expanded our large data communications product line with the addition of a new, ultra fast SDLC controller. And, there are a number of important intro- ductions in our Network, Security and Special Products categories.

That's just half the story, though. This handbook is for our compo- nent products only (including board-level solutions based on our LSI disk controllers). Separate handbooks and literature are available for our systems products. We urge you to use order forms at the front of this book to order your copies of the following:

Industrial Automation Handbook: Introduces The WEDGET~ our new 100 module family of Eurocord microcomputer systems based on 8085A18088l8086 processors and designed for command and control applications in an automated factory environment.

SuperMicro1600 Systems Brochure: Our 16-bit desktop computers, designed to improve programmer efficiency by functioning as low cost, high performance Pascal and Ada development systems, are explained in detail.

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Functional Index

FILE MANAGEMENT PRODUCTS. . . .. 11

Part Number Hard Disk Controllers WD1000 WD1001 WD1002 WD1100 WD1010 Hard Disk Support WD1011 WD1012 WD1014 WD1050 Floppy Disk Controllers FD176X-02 FD1771-0'1 FD1771-0'1 FD1781/FD1781-01 FD179X-02 FD179X WD279X-02 Floppy Disk Support WD1691 DM1883 A/B WD2143-03 WD9216-00/9216-01 Page Winchester Disk Controller ... " 13 Winchester Disk Controller ... " 21 Winchester Disk Controller . . . .. 31

Winchester Controller Chips ... " 33 Winchester Disk Controller ... " 77 Winchester Data Separator Device ... "... 83

Write Precompensation Device ... " 85 Buffer Manager/ Error Correction Device ... " 87 SMD Controller/Formatter. . . .. 93

Floppy Disk Formatter/Controller Family .. . . .. 99

Floppy Disk Formatter/Controller .... , ... " 123 Application Notes ... , ... 143

Floppy Disk Formatter/Controller ... , ... " 151 Floppy Disk Formatter/Controller Family ... 173

Application Notes ... 195

Floppy Disk Formatter/Controller Family ... 211

Floppy Support Logic (F.S.L.) ... 233

Direct Memory Access Controller ... 241

Four Phase Clock Generator ... 253

Floppy Disk Data Separator - FDDS ... 257

CRT CONTROLLERS ... 261

Part Number Page WD8275 ... 263

WD8276 ... 287

DATA COMMUNICATIONS ... 305

Part Number TR1402/TR1602 TR1863/TR1865 TR1402/TR1602/ TR1863/TR1865 WD1983 WD8250 WD2123 BR1941 WD1943/WD1945 PR1472 PT1482 Page Data Communication Protocol Definitions ... 307

Universal Asynchronous Receiver/Transmitter (UARn ... 311

Universal Asynchronous Receiver/Transmitter (UARn ... 321

Application Notes ... 333

(BOARn Bus Oriented Asynchronous ReceiverlTransmitter ... 345

Asynchronous Communications Element ... 357

DEUCE Dual Enhanced Universal Communications Element ... 373

Dual Baud Rate Clock ... 389

Dual Baud Rate Clock ... 397

I (PSAR) Programmable Synchronous & Asynchronous Receiver ... 405 (PSAn Programmable Synchronous & Asynchronous Transmitter ... " 419

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UC1671 WD1931 WD193X WD1931/WD1933 WD1993 WD1984

ASTRO ... 433

Asynchronous/Synchronous Receiver/Transmitter ... 447

Synchronous Data Link Controller Family ... 467

Compatibility Application Notes ... 485

Arinc 429 Receiver/Transmitter and Multi·Character Receiver/Transmitter ... 509

Multi·Character Synchronous/ Asynchronous Receiver/Transmitter ... 525

SECURITY PRODUCTS . ... 537

Part Number WD2001/WD2002 WD2001/WD2002 Page Data Encryption Devices ... 539

Applications Note ... 551

Cipher Feedback Cryptography Technical Note ... 559

MICROCONTROLLERS ... 561

Part Number Page WD51 Irrigation Controller ... 563

WD55 Industrial Timer/Controller ... 571

WD4200IWD4210 and WD4320/WD4321 Single Chip N·Channel Microcontrollers ... 585

4 Bit Microcomputers ... 609

SPECIAL PRODUCTS. . . . 611

Part Number WD1801 WD1802 WD2412 Page Octal Comparator ... 613

Octal Comparator. . . 617

Time of Day Clock ... 621

MEMORY PRODUCTS ... 629

Part Number FR1502 WD1510-00,01 WD1511 WD501 0 WD5869 WD74HC200 WD8206 WD8207 Page First·ln/First·Out Buffer Register ... 631

LIFO/FIFO Buffer Register ... 637

LIFO/FIFO Support Device ... 641

Single/Dual Read Content - Addressable Memory ... 645

Dynamic Shift Register ... 649

256 x 1 CMOS Static RAM ... 653

Error Detection and Correction Unit ... 657

Advanced Dynamic RAM Controller ... 677

LOGIC ARRAYS ... 679

Part Number WD1820 WD1840 Page Logic Array Device ... : ... '. . . . 681

Logic Array Device . . . 687

NETWORK PRODUCTS ... 691

Part Number WD2501/2511 WD2520 WD2840 Page Packet Network Interface (LAP/LAPB) ... 693

CCITT #7 Data Link Controller ... 705

Local Network, Token Access Controller. . . 707

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Part Number Page

WD51 ... 563

WD55 ... 571

WD1000 ... 13

WD1001 ... 21

WD1002 ... 31

WD1010 .. " ... 77

WD1011 .. "... 83

WD1012 .. "... 85

WD1014 .. " ... 87

WD1050 ... 93

WD1100 ... 33

TR1402/1602 ... 311

PR1472 ... 405

PT1482 ... 419

WD1502 ... 631

WD1510 ... 637

WD1511 ... 641

UC1671 ... 433

WD1691 ... 233

FD176X ... " . . . .. 99

FD1771 ... 123

FD1781 ... 151

FD179X ... 173

WD1801 ... 613

WD1802 ... 617

WD1820 ... 681

WD1840 ... 687

TR1863/1865 ... 321

DM1883 .. " ... 241

Numerical Index

Part Number Page WD1931 ... 447

WD193X ... 467

BR1941 ... , 389

WD1943/1945 ... 397

WD1983 ... 345

WD1984 ... 525

WD1993 ... 509

WD2001/2002 . . . 539

WD2123 ... 373

WD2143 ... 253

WD2412 ... 621

WD K2500 1 ... 719

WD2501 ... 693

WD2511 ... 693

WD2520 ... 705

WD279X ... 211

WD2840 ... 707

WD4200/4210 . . . .. 585

WD4320/4321 ... 585

WD5010 ... 645

WD5869 ... 649

WD74HC200 ... 653

WD8206 ... 657

WD8207 ... 677

WD8275 ... 263

WD8276 ... 287

WD8250 ... 357

WD921&o0/921&01 ... 257

4 Bit Microcomputers ... 609

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WESTERN DIGITAL

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Quality/Reliability To Leading Edge Technology

QUALITY PROGRAM DESCRIPTION

The Quality Organization shown in Figure 2 assures compliance to design control, quality and reliability specifications, pursuant to corporate policy.

CORPORATE QUALITY POLICY

It is the policy of Western Digital Corporation that every employee be committed to quality excellence in producing products/processes which conform to acceptable requirements. The total quality program is managed and monitored by the quality assurance organization. Quality assurance is chartered to review marketing product requirements, qualify hardware and software designs, certify manufacturing operations and monitor performance/control conformance to product specifications.

Primary responsibility for execution for the quality program rests with functional organizations to design, produce and market high quality and high reliability products specified to our customers.

LSI QUALITY ASSURANCE PROGRAM HIGHLIGHTS

• LSI manufacturing assurance provisions are derived in part from MIL-M-38510 and MIL-STD- 883B as applied to high grade commercial components.

• All process raw materials used in the Mask/Wafer fabrication and assembly operations are monitored by Material Assurance.

• Material Assurance maintains a thorough control of incoming material and has developed unique

"use/stress tests" (look ahead sample build acceptance) which critical material must pass before acceptance.

• The Product Assurance Department continuously monitors the internal and external manufacturing flow (shown in Figure 1) and issues process control reports displaying detailed data and trends for the associated areas.

Document control is an integral part of Product Assurance. All specifications are issued and controlled by this activity.

The Western Digital Malaysian assembly operation uses specifications and quality control provisions controlled by Document Control. Indicators of Malaysia quality are reviewed weekly.

Purchased FAB and assembly operations are individually qualified and are certified against standard specifications during vendor qualification and monitored against reliability criteria.

Defect control within the process assures the highest levels of built-in reliability.

• Quality audits and gates are located throughout the manufacturing process in order to assure a stable process and thus, a quality product to our customers. Figure 1 illustrates the manufacturing/

screening/inspection flow diagram and identifies the steps as they relate to the production of LSI devices.

• Testing assures quality margins through 100%

testing by manufacturing and, in addition, all products must pass a specified AQL sample test performed by QA at maximum operating temperature as follows:

Outgoing Quality Levels

SUBGROUPS INSPECTION LEVEL Subgroup 1 - Final 100% Electrical

Audit @ Max °C 0.5 AQL*

Subgroup 2 - Visual (Marking, Lead Integrity, Package, Verify customer

shipper) 1.0 AQL

Subgroup 3 - Shipping Visual Audit 1.0 AQL

"The double sampling techniques used allow considerably better AQL's in most all cases.

• LSI devices are 100% tested on industry standard test systems like that shown below. Quality outgoing testing (auditing) is done on the Fairchild Sentry Series 20 where possible to allow better correlation with customers.

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Ceramic

Starting Material Receiving Inspection Design and Mask Fabrication

Wafer In-Process Audits!

Defects Control (See Table 1)

Base Seal Inspection

Wire Bond Inspection Precap Inspection

~

~-5Ptlonal-

- - --;:.:

StaticlDynamlc

I

Burn-In I

100% Electrical

I

Test I

I Burn-In Brand I I

Shipping Audit Ship By Customer Specified Carrier

..

---~

Final Assembly Inspection

100% Stabilization Bake Plastic 125°C, 24 hrs.

Ceramic 150°C, 24 hrs.

100% Temperature Cycle Plastic - 55°C to + 125°C

10 cycles

Ceramic - 65°C to + 150°C 10 cycles

Gross Leak (.65 AQL) Ceramic

Fine Leak Test (.65% AQL)

Solder Dip Leads Lead Inspection

Cut and Form Inspection

100% Electrical Test

Final Test Audit - 0.5 AQL

Reliability Monitors (Table 3 & 4)

LEGEND

Optional Offshore Assembly Outgoing Inspection

Assembly Incoming Inspection

o

Manufacturing operation

o

Manufacturing Inspection Gate

o

Quality Assurance Audit

'\J Quality Assurance Gate

Figure 1 LSI PRODUCTION FLOW

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Reliability Means Lasting Value

• DESIGNING FOR RELIABILITY

The production release procedure for an LSI device is designed to assure maximum reliability With a Quality checklist for:

[B'" Test program qualifications lB'"' Characterization report lB'"' Field test (Beta Test) report lB'"' Reliability Ufetest Qualifications lB'"' Infrared Thermal Analysis IB" Static Protection

All new devices and major process changes must pass reliability qualification before incorporation into production using the criteria defined in Tables 2-4.

The infrared microscope shown on the right assures optimum burn-in temperatures and margins of safety.

The dynamic burn-in system shown on the right is one of two custom designed systems which assure protective device isolation during burn-in.

• MAINTAINING RELIABILITY IN PRODUCTION Process defects control are defined to continually measure built-in reli'ability, as measured by the following criteria:

TABLE 1 PROCESS RELIABILITY CONTROL METHOD Subgroup 1 - Defects Control

a. Oxide Integrity Non-destructive

bubble test

b. Polysilicon Integrity SEM Analysis

Subgroup 2 - Electro-Migration Control

Metal Step Coverage M I L-STD-883

Method 2018 Subgroup 3 - Defect Density Critical layers

Field Gate Contact Metal Subgroup 4 - Passivation/Insulation

Integrity MIL-STD-883 Method

2021

CONDITION

Pinhole defect density Visual

SEM Analysis

Visual of Photo defects (Defects/in2)

Visual of Pinhole defect density

'Inspection intervals are defined by the in·line process control data reviewed on a lot·by-Iot basis.

SAMPLE*

5 wafers 5 wafers 5 wafers 8 wafers each layer

Final Silox 5 wafers Intermediate

5 wafers

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• PROGRAMS TO ASSURE OPTIMUM RELIABILITY

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Improved levels of reliability are available under custom reliability programs using static and dynamic burn·in to C further improve reliability. These programs focus on MaS failure mechanisms as follows:

~

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~ :IJ FAILURE MECHANISMS IN MaS

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FAILURE EFFECT ON

MECHANISM DEVICE

Slow Trapping Wearout

Contamination Wearout!

Infant

Surface Charge Wearout

Polarization Wearout

Electromigration Wearout

Microcracks Random

Contacts Wearout!

Infant

Oxide Defects Infant!

Random Electron Injection Wearout

Temperature Acceleration of Failure

The Arrhenius Plot defines a failure rate propor·

tional to exp( - Ea/kt) where Ea is the activation energy for the failure mechanism. The figure on the right indicates that lower activation energy failures are not effectively accelerated by tem·

perature alone; hense, maximum voltage operation is selectively applied to optimize the burn·in process.

Static Bum-In (125°C - 48 hours or 160 hours) Provided on a sample basis for process monitor/control of 0.5 eV - 1.0 eV failure mechanisms. 100% static burn·in may be specified at an additional cost. However, static burn·in is considered only partially effective for internal LSI gates at logic "0" levels.

Dynamic Burn-In (Pattern test/125°C - 8 hours to 160 hours)

Accelerated functional dynamic operating life effectively controls internal MaS gate defects buried from external pin access. The input pattern is optionally pseudo-random or fixed pattern programmable to simulate 1000-3000 hours of field operation at maximum operating voltage(s).

High-Rei "K" Testing Program

General conformance to MIL·STD-883B method 5004.4, Class B with static Burn·ln (Dynamic Burn·

In may be specified as an option).

ESTIMATED SCREENING

ACTIVATION ENERGY METHOD

1.0eV 1.4eV 0.5-1.0eV 1.0eV 1.0eV

-

- 0.3eV

-

10'·

10' 10·

en

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10'

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Static Burn·ln Static Burn·ln Static Burn·ln Static Burn·ln Dynamic Burn·ln 100% Temp. Cycling Dynamic Burn·ln Dynamic Burn·ln at max. voltage Low Temp. Voltage Operating Life

50 75 100 125 150 175 200 250 TEMPERATURE (0C)

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lSI RELIABILITY STANDARDS

TABLE 2 STANDARD RELIABILITY LEVELS

TEST METHOD CONDITION FAILURE

Infant Static 125°C - 160 hrs. <0.5%

Mortality Burn-In

(see note)

Long Term Dynamic 125°C - 1000 hrs. <.05%/1000 hrs.

Failure Rate Life Test @ 55°C

60% Confidence

"NOTE: Devices failing the infant mortality target remain on burn-in until acceptable failure rates are obtained.

TABLE 3 GROUP A DEVICE RELIABILITY MONITORS

TEST METHOD CONDITIONS LTPD

Subgroup 1

a. Internal Visual 15

b. Thermal Shock 1011 Test Failure Used (cond. B orC)

c. Bond Strength 2011 Test Failures (cond. B)

d. Die Shear Strength 2019 Test Failures

. - - - - - - - - - - ---_ .... "--~---"--.--.-~ - -

Subgroup 2

a. Seal- Gross Leak Fluorocarbon detection 10 - 3 15

atm/cc/sec

b. Seal - Fine Leak 1014 Test Condition A

!-- - ----"-" . . - - - -- - - -..-. - - - -

Subgroup 3

a. Rotating Steady State Life Test 1005 Static 160 hr. Burn-In 125°C 5 plus 125°C Lifetest - 1000 hrs.

b. Electrical Parameters - Final electrical @ 25°C (with data @ 70°C)

TABLE 4 GROUP B PACKAGE RELIABILITY MONITORS

TEST METHOD CONDITIONS LTPD

Subgroup 1

a. Thermal Shock 1011 Test Condition B or C 15

b. Temperature Cycling 1010 Test Condition B or C c. Seal - G ross Leak - Fluorocarbon detection 10 - 3

atm/cc/sec d. Seal - Fine Leak (ceramic) 1014 Test Condition A e. Electrical Parameters - Electrical at max -C f. 85/85 Moisture Resistance - 85% RH/85°C for 1000 hours

(plastic only) PDA = 10%

g. Electrical Parameters - Final electrical @ 25°C

---~---c--- ^"---- - - - - - - - -

Subgroup 2

a. High Temp. Storage 1008 Test Condition B or C

b. Mechanical Shock 2002 Test Condition B 15

c. Seal - G ross Leak - Fluorocarbon detection 10 - 3 atm/cc/sec

d. Seal - Fine Leak 1014 Test Condition A

(ceramic)

e. Electrical Parameters - Final electrical @ 25°C/max. C

- - - _ . -~---~-- --- - - e - - - - ---.---~---.-

Subgroup 3

a. Lead Integrity 2004 Test Condition B2 15

(Lead Fatigue)

b. Seal - G ross Leak - Fluorocarbon detection 10 - 3 atm/cc/sec

c. Seal - Fine Leak 1014 Test Condition A

(ceramic)

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• Systems Quality

• New Product Qualification

• System Test Qualification

• Software Qualification

"Systems DeSign Control"

WESTERN DIGITAL CORPORATION CHIEF EXECUTIVE

• LSI Qualification

• Burn-In/Stress Requirements

• Reliability Monitor Data

• Reliability Testing

• Document Control

• Wafer Defects Control

• Subsidiary/Offshore QC

• Process Qualification

• Incoming QC

• Vendor Quality

• LSI Burn-In

• LSI Package Monitors

• Precap Visuals (883 optional)

• 100% Test Audit

• Failure Analysis

• Package Qualification

• Calibration Control

"LSI DeSign Control" "Manufacturing Assurance"

Figure 2 QUALITY ORGANIZATION

Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change specifications at anytime without notice.

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WESTERN DIGITAL

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Announcing Burn-In Program Availability/Warranties

Western Digital now supports customer burn-in requirements for both static and dynamic burn-in under the strict control of the QA-Reliability organization.

This burn-in provides high performance 125°C static and dynamic burn-in for 8-160 hours to eliminate infant mortality and improve reliability. This process is executed using custom modified 32Bit AEHR test commercial burn-in equipment which provide monitored fixed pattern or pseudorandom burn-in with power supply and resistor device pin isolation.

LSI dynamic burn-in is verified in all cases by the design engineer for proper functioning. LSI Chip sets are also individually burned-in with dynamic equiva- Ilency to assure high performance bundled reliability.

The warranty on the program will optionally provide certificate of compliance to standard or custom designed bum·in programs and guarantee <.05%/Khrs failure rate.

CAUTION

Using outside burn-in methods not certified as acceptable by Western Digital may result in voided warranty, due to mishandling, junction temperature stress, or electrical damage. Further, since most burn-in houses do not support testing, catastrophic system condition can result in substantial damage before a problem is identified.

One consistent problem experienced with outside LSI burn-in houses can cause reliability problems;

namely, parallelling totem pole MOS outputs, where the output states are not predictable, can cause a single (or a few) device(s) to sink all the current from the other devices on the burn-in tray - electromigration or current zaps are both possible.

Western Digital burn-in diagrams, dated after 1/1/82, must be used exactly as shown and will be provided upon request.

SEE YOUR LOCAL REPRESENTATIVE FOR COSTS AND ORDERING INFORMATION ON THIS NEW PROGRAM.

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InformatIon furnIshed by Western DIgItal CorporatIon IS believed to be accurate and relIable. However, no responSIbilIty IS assumed by Western DIgital CorporatIon for Its use: nor for any Infflngements of patents or other fights of thIrd partIes whIch may result from ItS use. No lIcense is granted by implicatIOn or otherWIse under any patent or patent rIghts of Western DIgItal CorporatIon Western DIgItal CorporatIon reserves the fight to change specifIcatIons at anytIme wIthout notIce

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WESTERN DIGITAL

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Hi-Rei "K" Testing Program

FEATURES

GENERAL CONFORMANCE TO MIL-STD-883B, METHOD 5004.4, CLASS B (SEE COMPARISON ON FOLLOWING PAGES)

• INCLUDES:

PRECAP VISUALS SEAL INTEGRITY POWER CONDITIONING ENHANCEMENT OPTIONS

INITIATE LOT PACKAGE PROBED WAFERS TRAVELER

SCRIBE/SAW

BREAK/SORT

INSPECT

CHIPBOND

INSPECT

WIRE BOND

INSPECT

CLEAN/BAKE/SEAL TEMP CYCLE 10 CYCLES

- 65'/ + 150'C STABAKE 24 HRS 150'C

GENERAL DESCRIPTION

Western Digital's Hi-Rei "K" program is designed to provide high reliability devices for extended temperature environments. Individual enhancements may be specified to meet a customer's requirements.

CERTIFICATE OF CONFORMANCE

OC AUDIT

FINE LEAK

GROSS LEAK

CUT/FORM LEADS

PRE BURN·IN ELECTRICALS BURN-IN 160 HRS @ 125°C FINAL TEST

FINAL TEST 0.5% AOL

BRAND

MOVETO FINISHED GOODS PACK

SHIP VIA CUSTOMER SPECIFIED CARRIER

HI-REL "K" PROGRAM FLOW DIAGRAM

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COMPARISON OF MIL·STD·883 AND HI·REL "K" TEST PROGRAM MIL·STD·883B, METHOD 5004.4, CLASS B

3.1.1 Internal Visual Method 2010.3 Test condition B

3.1.2 Stabilization Bake Method 1008.1 Test condition C 24 hours at 150°C 3.1.3 Temperature Cycling Method 1010.2, Test condition C

- 65°C to 150°C for 10 cycles, with 10 minutes dwell and 5 minutes maximum transfer time 3.1.4 Constant Acceleration

Method 2001.2, Test condition E. 30,000 G stress level

3.1.5 Visual Inspection

Visual inspection for catastrophic failures after screens

3.1.6 Seal Method 1014.2

(a) Helium fine leak - Test condition A1. Bomb condition 2 hours at 60 psig. Reject limit 5 x 10-⁸ torr

(b) Flourocarbon gross leak - Test condition C 3.1.9 Interim (pre·burn·in) Electricals

Per applicable device specification 3.1.10 Burn·in Test

Method 1015.2160 hours @ 125°C 3.1.13 Interim (Post burn·in) electricals Per applicable device specification 3.1.15 Final Electrical Test (a) Static Tests

(1) 25°C

(2) Minimum and Maximum Operating Temperatures

(b) Dynamic and Switching Tests at 25°C (c) Functional Tests at 25°C

3.1.17 Qualification or Quality Conformance Inspection and Test Sample Selection 3.1.18 External Visual

Method 2009.2

WESTERN DIGITAL RELIABILITY ENHANCEMENT OPTIONS

100% Temperature Testing

Level ... - 40° to + 85°C . . . - 55° to + 125°C Thermal, Shock (Liquid to Liquid)

Level. ... 0° to + 100°C, 15 cycles . . . - 55° to + 125°C

HI·REL "K" TEST

All Hi·Rel "K" devices receive 100% inspections prior to lid seal. These inspections together com·

prise criteria comparable to Mil·Std·883, method 2010.3, test condition B.

Same

Not Done Unless Specified

Same Same

Same

Preburn·in test at 25°C. Must meet requirements of device data sheets.

Same

Burn·in equipment isolate failures automatically to assure no harmful interaction.

Same

Not done unless defined using method 5005 as a guide.

Same

Extended High Temperature Storage

+ 150°C for 24 hours standard, other time/tempera·

ture storage requirements available as required . Dynamic Bum·ln

Per note previously supplied .

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Part Number Hard Disk Controllers

WD1000 WD1001 WD1002 WD1100 WD1010 Hard Disk Support

WD1011 WD1012 WD1014 WD1050

Floppy Disk Controllers FD176X-02

FD1771-01 FD1771-0'1 FD1781/FD1781-01 FD179X-02 FD179X WD279X-02 Floppy Disk Support

WD1691 DM1883A/B WD2143-03 WD9216-00/9216-01

File Management Products

Page

Winchester Disk Controller. . . .. 13 Winchester Disk Controller ... , 21 Winchester Disk Controller ... , 31 Winchester Controller Chips . . . .. 33 Winchester Disk Controller ... , 77

Winchester Data Separator Device ... 83 Write Precompensation Device . . . .. 85 Buffer Manager/Error Correction Device ... , 87 SMD Controller/Formatter. . . .. 93 Floppy Disk Formatter/Controller Family ... , 99 Floppy Disk Formatter/Controller ... , 123 Application Notes ... 143 Floppy Disk Formatter/Controller ... , 151 Floppy Disk Formatter/Controller Family ... , 173 Application Notes ... 195 Floppy Disk Formatter/Controller Family ... 211 Floppy Support Logic (F.S.L.) ... 233 Direct Memory Access Controller ... 241 Four Phase Clock Generator ... 253 Floppy Disk Data Separator - FDDS ... 257

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WESTERN DIGITAL

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WD1000 Winchester Disk Controller

C;ENERAL DESCRIPTION

The WD 1000 is a stand-alone, general purpose Winchester controller board designed to interface up to four Win- chester disk drives to a host processor. The drive signals are based upon the floppy look-alike interface available on the Shugart Associates' SA 1000, the Seagate Technology 8T506, the Quantum Q2000, and other compatible drives.

All necessary buffers and receivers/drivers are included on the board to aUow direct connection to the drive. Either a 34 pin (5%" drive) or 50 pin (8" drive) connector is provided, as well as four 20 pin data connectors.

Communications to and from the host computer are made via a separate computer access port. This port consists mainly of an 8 bit bi-directional bus and appropriate control signals. All data to be written to or read from the disk, status information, and macro cammands are transferred via this 8 bit bus. An on board sector buffer allows data transfers to the host computer independent of the actual data transfer rate of the drive.

The WD 1000 is based upon a proprietary chip set, the VVD 1100, specifically designed for Winchester Control.

.

- FEATURES

• BUILT-IN DATA SEPARATOR

• BUILT-IN WRITE PRECOMPENSATION LOGIC

• DATA RATES UP TO 5 MBITS/SEC

• CONTROL FOR UP TO 4 DRIVES

• CONTROL FOR UP TO 8 R/W HEADS

• 1024 CYLINDER ADDRESSING RANGE

• 256 SECTOR ADDRESSING RANGE

• CRC GENERATIONIVERIFICATION

• AUTOMATIC FORMATIING

• 128, 256, OR 512 BYTES PER SECTOR (ROM SELECTABLE)

• UNLIMITED SECTOR INTERLEAVE CAPABILITY

• OVERLAP SEEK CAPABILITY

• IMPLIED SEEK ON ALL COMMANDS

• AUTOMATIC RETRIES ON ALL ERRORS

• AUTOMATIC RESTORE AND RE-SEEK ON SEEK

!:RROR

• 8-BIT HOST INTERFACE

• O°C to 50°C OPERATION

ORGANIZATION

The WD1000 has seven on board connectors. These connectors consist of a power connector, host interface connector, drive control connector, and four high speed data cable connectors.

The drive control cable is daisy-chained to each of the four drives. Although there is space for two drive control connectors, only one would normally be used for any particular configuration.

The drive data connectors carry differential signals and are radially connected. Up to four drives can be accommo- dated by the WD1000.

The host interface connector provides interface signals that are compatible with most microprocessors and mini- computers.

WD1100

For those who want to design their own board around the WD1100 chip set, Western Digital can provide schematics, artwork, and programming information. Western Digital also has a complete staff of Applications Engineers to provide additional support. For further information please contact your local representative, or our main plant listed on page 8 .

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SPECIFICATIONS Encoding method:

Cylinders per Head:

Sectors per Track:

Heads:

Drive Selects:

Step rate:

Data Transfer Rate:

Write Precomp Time:

Sectoring:

Host Interface:

Drive Capability:

Drive Cable Length:

Host Cable Length:

Power Requirements:

Ambient Temperature Operating:

Relative Humidity:

MTBF:

MTTR:

Length:

Width:

Height:

Mounting Centers:

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WD1000 BLOCK DIAGRAM

MFM Up to 1024

Up to 256 (512 byte sec) 8

4

10 uS to 7.5 mS (0.5 mS increments) 4.34 Mbits/sec or 5.000 Mbits/sec 10 nanoseconds Soft

8 Bit bi-directional bus 10 ilLS" Loads 10 ft. (3 M) max.

3 ft. (1 M) max.

+ 5V ± 5%, 3.0A Max. (2.5A typ.) - 8 to -18V, 50 rnA * O°C to 50°C (32 F to 122 F) 20% to 80%

10,oooPOH 30 minutes 9.9 in. (24.9 cm) 6.8 in. (17.1 cm) 0.75 in. (1.9 cm)

6.375 x 9.375 in. (16 x 23.6 cm)

HOST INTERFACING

The WD1 000 is designed to easily interface to most micro computers and mini-computers. All interfacing is done through the Host Interface Connector (J5). The interface is very similar to Western Digital's family of Floppy Disk Controllers. The only exception is the inclusion of the WAIT line.

Walts

The WAIT control line goes true whenever' either of the following are true:

• The WD1000 is accessing data internally to send to the host during a read operation

• The WD1000 has not accepted the data from the host during a write operation.

The definition of the WAIT line is very similar to the WAIT signal found on many popular processors. WAIT is also similar to the REPLY signal on Western Digital and other processors.

* Optional - V Supply Available.

WAIT will not necessarily make a transition for each access to the WD 1000. When the WD 1000 can return the requested data within 100 nS, there will be no transition of the WAIT line. This should be interpreted as an instant REPLY on Western Digital Processors.

(28)

If the WD1000 cannot return the requested data within 100 nS, it will assert its WAIT line. The period of the WAIT signal will vary from 750 nS to 6 uS with 1.25 uS being about average. The, period of the WAIT only approaches 6 uS during a read or write which happens immediately after a command is written to the command register. This means that longer waits may be encountered during the first read or write to any WD1000 register if that first read or write happens within approximately 6 uS of a command being issued.

During the time that WAIT is asserted, the host system must hold all of its strobe and address lines stable. On write operations, the DAL lines must also be held stable.

HOST INTERFACE CONNECTOR

SIGNAL GROUND SIGNAL PIN SIGNAL NAME

2 1 DALO

4 3 DAL1

6 5 DAL2

8 7 DAL3

10 9 DAL3

12 11 DAL5

14 13 DAL6

16 15 DAL7

18 17 AO

20 19 A1

22 21 A2

24 23 CS

26 25

28 27

30 29

32 31 Not Connected

34 33

-v

36 35 INTRQ

•

The user can modify the timing of the wait signal by select·

ing a jumper. The WD1000 is shipped with a jumper (or trace) between E4 and E5. This enables waits as soon as the CS signal is asserted. This timing is a requirement for some processors and compatible with most. If the host system requires the WAIT signal to be asserted only when RE or WE are asserted in conjunction with CS, the trace at E4 and E5 should be cut and a jumper should be installed between E4 and E3.

The Host Interface connector (J5) consists of an eight bit bi·directional bus, three bit address bus, and seven control lines. All commands, status, and data are transferred over this bus. See Table 1:

TABLE 1 DESCRIPTION

8 bit bi·directional Data Access Lines. These lines remain in a high·impedance state whenever the CS line is inactive.

These three Address Lines are used to select one of eight registers in the Task File. They must remain stable during all read and write operations.

When Card Select is active along with RE or WE, Data is read or written via the DAL bus. CS must make a transition for each byte read from or written to the task file.

When Write Enable is active along with Cs, the host may write data to a selected register of the WD1000.

When Read Enable is active along with Cs, the host may read data from a selected register of the WD1000.

Upon receipt of a Cs, the WAIT line may go active. It returns to the inactive state when the DAL lines are valid on a read, or data has been accepted on a write.

Optional - V input from host supplies - 8 to -15V to the on·board - 5 Volt regulaton (VRI). This power input is also available on J6, pin 2. - V is not required if DC/DC convertor (PSI) is used.

The INTerrupt ReQuest Line is activated whenever a command has been completed. It is reset to the inactive state when the Status Register is read, or a new command is loaded via the DAL lines .

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(29)

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HOST INTERFACE CONNECTOR (Continued) SIGNAL GROUND SIGNAL PIN SIGNAL NAME

I

38

I

37 DRO

I

40 39 MR

I ⁴¹ Not Connected

42 Not Connected

I

43-50

Note: Grounds

DRIVE CONTROL CONNECTORS

The drive control connector is a (relatively) low speed bus that is daisy chain connected to each of the drives (up to four) in the system. To properly terminate each TTL level output signal from the WD1000, the last drive in the daisy chain should have a 220/330 ohm line termination resistor pack installed. All other drives should have no termination.

See Tables 2 and 3:

34 PIN DRIVE CONTROL CONNECTOR TABLE 2

SIGNAL SIGNAL SIGNAL

GROUND PIN 1/0 NAME

1 2 0 RWC

3 4 0 Head Select 2"

5 6 0 Write Gate

7 8 I Seek Complete

9 10 I TROOO

- - - -

11 12 I Write Fault

13 14 0 Head Select '0

15 16 NC

19 20 I Index

21 22 I Ready

23 24 0 Step

25 26 0 Drive Select 1"

29 30 0 Drive Select 3

33 34 0 Direction Tn

DESCRIPTION

The Data ReOuest line is activated whenever the sector buffer contains data to be read by the host, or is awaiting data to be loaded by the host. This line is reset whenever the Data Register is read from or written to. The DRO line will continue to toggle until the buffer is exausted or until a write or read is performed on the Cylinder Low register.

The Master Reset line initializes all internal logic on the logic on the WD1000. Sector Number, Cylinder Number and SDH are cleared, stepping rate is set to 7.5 mS, Write Precomp is set to cylinder 128 and Sector Count is set to 1. The DRO line is reset and the INTRO line is set.

+ 5V 8 power pins for regulated + 5 volts. This power input is also available on J6, pin 3.

Even numbered pins (2-40) are to be used as signal grounds. Power ground is available on J6, pin 1.

50 PIN DRIVE CONTROL CONNECTOR FOR SA1000

TYPE INTERFACE TABLE 3

SIGNAL SIGNAL SIGNAL

GROUND PIN 1/0 NAME

1 2 0 RWC

5 6 NC

7 8 I Seek Complete

9 10 NC

11 12 NC

13 14 0 Head Select (5

15 16 NC

19 20 I Index

21 22 I Ready

23 24 NC

29 30 0 Drive Select· 3"

33 34 0 Direction Til

35 36 0 Step

37 38 NC

39 40 0 Write Gate

41 42 I TROOO

43 44 I Write Fault

45 46 NC

47 48 NC

49 50 NC

(30)

•

DRIVE CONTROL SIGNAL DESCRIPTIONS RWC

When the Redluce Write Current line is activated with write gate, a lower write current is used to compensate for greater bit packing density on the Inner cylinders. The RWC line Is activated when the cylinder number is greater than or equal to four times the contents of the Write Precomp Reg- ister. This output is valid only during Write and Format commands.

Write Gate

This output signal allows data to be written on the disk.

Seek Complete

Informs the WD1000 that the head of the selected drive has reached the desired cylinder and has stabilized. Seek Com- plete is not checked after a SEEK command, thus allowing overlapped seeks.

Track 000

Indicates that the R/W heads are positioned on the outer- most cylinder. This line is sampled immediately before each step is issued.

Write Fault

Informs the WD1000 that some fault has occurred on the selected drive. The WD1000 Will not execute commands when this signal is true.

HSOHS2

Head Select lines are used by the WD1000 to select a speci- fic R/W head on the selected drive.

index

Is used to indicate the index point for synchronization during formatting and as a time out mechanism for retries.

This signal should pulse once each rotation of the disk.

Roady

In'forms the WD1000 that the desired drive is selected and that its motor is up to speed. The WD1000 will not execute commands unless this line is true.

Step

This line is pulsed once for each cylinder to be stepped.

The direction of the step will be determined by the DIREC- TION line. The step pulse period is determined by the internal stepping rate register during implied seek operations or explicitly during Seek and Restore commands. During auto restore, the step pulse period is determined by the SEEK COMPLETE time from the drive.

Direction Tn

Determines the direction of motion of the R/W head when thE~ step line is pulsed. A high on this line defines the direction as out and a low defines direction as in.

-

DS1DS4

These four Drive Select lines are used to select one of four possible drives.

DRIVE DATA CONNECTOR

Four data connectors (J1-4) are provided for clock Signals and data between the WD1000 and each drive. All lines associated with the transfer of data between the drive and the WD1000 system are differential in nature and may not be multiplexed. The data connectors are 20 pin vertical headers on tenth-Inch centers that mate with Burndy

#FRS2OBS. The cable used should be flat ribbon cable or twisted pair with a length of less than 10 feet. The cable pin-outs are per Table 4:

DATA CONNECTIONS AND DESCRIPTIONS TABLE 4 SIGNAL SIGNAL

GROUND PIN 110

2 1 I

4 3

6 5

8 7

9 0

10 0

11 12

13 0

14 0

15 16

17 I

18 I

19 20

DIFFERENTIAL DATA DRIVER/RECEIVER

HIIlH TRUE

AMD28LS31 or 15110A NOTE: ANY RS 422 DRIVER/RECEIVER PAIR WILL INTERFACE

Z,10512 FLAT RIBBON OR TWISTED PAIR

MAX 10 FT.

POWER CONNECTOR

SIGNAL NAME - Drive Selected

NC NC NC

+ Timing Clock - Timing Clock

GND GND

+ MFM Write Data - MFM Write Data

GND GND

+ MFM READ DATA - MFM READ DATA

GND GND

1. Open for AMD 21LS31 (8T&08) Clo .. d lor76110A(SA10001

HIIlH TftUE

A three pin molex connector (J6) is provided for power In- put to the board. The customer supplied mating connector housing Is Molex 03-09-1032. The pin-outs are as shown in Table 5:

TABLES

PIN SIGNAL NAME

1 GROUND

2 - 8 to -15 V unregulated 3 + 5 V regulated

(31)

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COMMANDS

The WD1000 executes five easy to use macro commands.

Most commands feature automatic 'implied' seek, which means the host system need not tell the WD1000 where the RJW heads of each drive are or when to move them. The controller automatically performs all needed retries on all errors encountered including data CRC errors. If the RJW head mis-positions, the WD1000 will automatically perform a restore and a re-seek. If the error is completely unre- coverable, the WD1000 will simulate a normal completion to simplify the host system's software.

Commands are executed by loading the command byte into the Command Register while the controller is not busy. (Controller will not be busy if it has completed the previous command.) The task file must be loaded prior to issuing a command. No command will execute if the Seek Complete or Ready lines are false or if the Write Fault line is true. Normally it is not necessary to poll these signals before issuing a command. If the WD1000 receives a command that is not defined in the following table, undefined results will occur.

For ease of discuSSion, commands are divided into three types which are summarized in Table 6:

TABLES TYPE COMMAND 7

I Rastore 0

I Seek 0

II Read Sector 0 III Write Sector 0

1 - .

III Format Track 0

ra-ro - STEPPING RATE 0000 = 10uS 0001 = O.SmS 0010 = 1.0mS 0011 = 1.SmS 0100 = 2.0mS 0101 = 2.SmS 0110 = 3.0mS 0111 = 3.5mS

o

= DMA Read Mode 6 0 1 0 0 1

o = Programmed 110 Mode 1 = DMAMode

NOTE:

5 0 1 1 1 0

BITS 4 3 2 1 1 r3 r2 r1 1 r3 r2 r1 0 0 0 0 1

1

0 0 0 0 0 0

1000 = 4.0mS 1001 = 4.5mS 1010 = 5.0mS 1011 = 5.5mS 1100 = 6.0mS 1101 = 6.5mS 1110 = 7.0mS 1111 = 7.5mS

0 rO ro 0 0 0

The DMA bit is used to position INTRa in relation to DRas during the read sector command. If the DMA bit is reset (0 = 0), the interrupt will occur before the first ORO. This allows the programmed 110 host to intervene and transfer the data from the sector buffer. If the DMA bit Is set (0 = 1), then the interrupt will occur only after the system OMA controller has transferred the entire buffer of data.

TYPE I COMMANDS

These commands simply position the RJW heads of the selected drive. Both commands have explicit stepping rate fields. The lower four bits of these commands form the stepping rate.

RESTORE

The Restore command is used to calibrate the position of the RJW head on each drive by stepping the head outward until the TRooo line goes true. Upon receipt of the Restore command, the Busy bit in the Status Register is set. Cylin- der High and Cylinder Low Registers are cleared. The lower four bits of the command byte are stored in the stepping rate register for subsequent implied seeks. The state of Seek Complete, Ready and Write Fault are sampled, and if an error condition exists, the Aborted command bit in the Error Register is set, the Error bit in the Status Register is set, an interrupt is generated and the Busy bit is reset.

If no errors are encountered thus far, the internal head position register for the selected drive is cleared. The TRooo line is sampled. If TRooo is true, an interrupt is generated and the Busy bit is reset. If TRooo is not true, stepping pulses at a rate determined by the stepping rate field are issued until the TRooo line is activated. When TRooo is activated, the Busy bit is reset and an interrupt is issued. If the TRooo line is not activated within 1023 stepping pulses, the TRooo Error bit in the Error Register and the Error bit in the Status Register are set, the Busy bit is reset and an interrupt is issued.

SEEK

The Seek command positions the RJW head to a certain cylinder. It is primarily used to start two or more concurrent seeks on drives that support buffered stepping. Upon receipt of the Seek command, the Busy bit in the Status Register is set. The lower four bits of the command byte are stored in the stepping rate register for subsequent implied seeks. The state of Seek Complete, Ready and Write Fault are sampled, and if an error .condition exists, the Aborted command bit in the Error Register is set, the Error bit in the Status Register is set, an interrupt is generated and the Busy bit is reset.

If no errors are encountered thus far, the internal head position register for the selected drive is updated, the direction line is set to the proper direction and a step pulse is issued for each cylinder to be read and an interrupt is issued. Note that the Seek Complete line is not sampled after the Seek command, allowing multiple seek operations to be started using drives with buffered seek capability.

TYPE II COMMANDS

This type of command is characterized by a transfer of a block of data from the WD1000 buffer to the host. This command has an implicit stepping rate as set by the last Re- store or Seek command.

The Read Sector command is used to read a sector of data from the disk to the host computer. Upon receipt of the Read command, the Busy bit in the Status register is set.

The state of Seek Complete, Ready and Write Fault are sampled, and if an error condition exists, the Aborted Command bit in the Error Register is set, the Error bit in the Status Register is set, and a normal completion is simulated.

CORPORA TID

1983

Components

Handbook

Western Di'gital

1983 Components

Handbook

Making The Leading Edge Work For You"

Western Digital: Update '83

Table of Contents

Functional Index

Numerical Index

WESTERN DIGITAL

c o R P o

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Quality/Reliability To Leading Edge Technology

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Reliability Means Lasting Value

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WESTERN DIGITAL

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Announcing Burn-In Program Availability/Warranties

WESTERN DIGITAL

c o R P o

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Hi-Rei "K" Testing Program

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File Management Products

WESTERN DIGITAL

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WD1000 Winchester Disk Controller

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