Microcomputer Components Data Book

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Microcomputer

Components

Data Book

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Zilog offers microcomputers in every form: from components and development systems to board-level products and complete general- purpose microcomputer systems.

This edition of the Zilog Data Book describes Zilog components, development systems, and microcomputer boards. You'll also find a section on the in-depth training courses now offered about most Zilog products.

Zilog components, the basic building blocks for our other microcomputer products, include the 8-bit Z80® Microprocessor and its family of intelligent peripherals, the Z8™ Family of Single-Chip Microcomputers, and the l6-bit

Microcomputers in Every Form

Z8000™ Microprocessor and its family of intelligent peripherals.

Zilog offers a wide variety of development environments, rang- ing from the inexpensive Z8 and Z8000 Development Modules to the more elaborate PDS 8000 and ZDS-l Development Systems to the ultra-sophisticated multi-user Z-LAB 8000 Development System.

In addition, the Z-SCAN 8000 provides in-circuit emulation for both the Z800 land 28002 Microprocessors.

Our 280 MCB Board Family offers a complete solution for pro- totype and production designs in which you don't want to design a microcomputer from scratch. This

iii

well-established family includes a Z80 CPU board, several types of memory boards, and boards for all types of digital and analog I/O. A complete set of card cages, enclosures, and other accessories makes this family easy to use.

The card at the beginning of the data book allows you to register for an on-going program to keep you informed of the latest developments at Zilog. New information will be published as "stand-alone" data sheets, also in this convenient 7" x 9" size. If you are interested in receiving this information as well as a handy binder to hold it in, simply fill out the card and return it to us.

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Microcomputer Boards ... 443

Z80 MCB ... 445

8

Z80 RMB ... 449

Z80 AIO/AIB ... 453

Z80 IOB ... 457

Z80 SIB ... 459

Z80PPB ... 463

Z80 PMB ... .465

Z80 MDC ... 467

Zilog Development Systems ... 473

ZDS-1I25 ... 475

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ZDS-l/40 ... 477

PDS 8000 . . . .. . ... .481

Z8 Development Module ... 485

Z8000 Development Module ... 489

Z-SCAN 8000 ... 493

Z80 PLZ ... 497

Z8 Software Development Package ... 499

Z8000 Softwdre Development Package ... 501

Z8000 Cross-Software Package ... 503

Zilog Technical Training ... 507

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Z80 Family

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Zilog ~

Zilog has become an industry leader, thanks to innovation in microcomputer concepts and integrated design exemplified in the Z80 Family of microcomputer products.

At Zilog, mnovahon means using proven, sophisticated mainframe and minicomputer concepts and translating them into the latest LSI technologies. Integration means more than designing an ever- greater number of funchons onto a single chip. Zilog integrates technologies-LSI design enhanced by advances in computer-based system architecture and system deSign technologies.

Zilog offers miCroprocessor solutions to computing problems:

from components and development systems to OEM board-level products and general-purpose microcomputer systems.

ThiS gUide to the Z80 Family of state-of-the-art microprocessors and mtelligent peripheral controllers demonstrates Zilog's continued support for the Z80 miCroprocessor and the other members of the Z80 product familY-d family first introduced m 1976 that continues to enjoy grow- ing customer support while family chips are upgraded to newer and ever-higher standards.

The design philosophy of all Z80 Family members IS to help eng meers deSign microcomputer systems with fewer components that have more functions per chip. The

Zilog Z80® Family Faster Z80B

Peripheral Controllers

March 1981

Z80 CPU offers many more features and functions than its competitor.

The Z8400 Z80 CPU Central Processing Unit has rapidly established itself as the most sophisticated, most powerful, and most versatile 8-blt microprocessor in the world. In addition to being source-code compatible with the 8080A microprocessor, the Z80 offers more mstruchons than the 8080A (158 vs. 78) and numerous other features that simplify hard- ware requirements and reduce programming effort while increasing throughput. The dual-register set of the Z80 CPU allows high-speed context switching and more effi- Cient interrupt processing. Two index registers give additional memory-addressing fleXibility and simplify the task of programmmg.

InterfaCing to dynamic memory is svnplified by on-chip, programmable refresh logiC. Block moves plus string- and bit-manipulation mstructions reduce programming effort, program Size, and execution hme.

The four traditional funchons of a microcomputer system (parallel I/O, serial I/O, co\mting/timmg, and direct memory access) are easily implemented by the Z80 CPU and the following well-proven family of Z80 peripheral devices:

Z80 PIO, Z80 SIO, Z80 DART, Z80 CTC, and Z80 DMA.

The easily programmed, dual- channel Z8420 Z80 PIO Parallel Input/Output Controller offers two 8-bit I/O ports with individual handshake and pattern recognihon

logiC. Both I/O ports operate in either a byte or a bit mode. In addition, this deVice can be programmed to generate interrupts for various status condihons.

All common data communica- tions protocols, asynchronous as well as synchronous, are remarkably well handled by the Z8440 Z80 SIO Serial Input/Output Controller. This dual-channel receiver/transmitter device offers on-chip parity and CRC generation/checking. FIFO buffering and flag- and frame-detection generation logic are also offered.

If asynchronous-only applications are required, the cost- effective Z8470 Z80 DART Dual Asynchronous Receiver/Transmit- ter can be used in place of the Z80 SIO. The Z80 DART offers all Z80 SIO asynchronous features in two channels.

Timing and event-counting functions are the forte of the Z8430 Z80 CTC Counter/Timer Controller.

The CTC provides four counters, each with indiVidually programmable prescalers. The CTC is a convenient source of programmable clock rates for the SIO.

With the Z8410 Z80 DMA Direct Memory Access Controller, data can be transferred directly between any two ports (tYPically, I/O and memory). The DMA transfers, searches, or search/transfers data in Byte-by-Byte, Burst, or Continuous modes. This deVice can achieve an impressive 2M bits per second data rate m the Search mode.

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~ Zilog

Features

2001·0210, 0211

• The instruction set contains 158 instructions.

The 78 instructions of the 8080A are included as a subset; 8080A software com- patibllity is mamtained.

• SlX MHz, 4 MHz and 2.5 MHz clocks for the Z80B, Z80A, and Z80 CPU result in rapid instruction execution wlth consequent high data throughput.

• The extensive instruction set mcludes string, bit, byte, and word operations. Block searches and block transfers together with indexed and relahve addressing result m the most powerful data handling capabilities in the microcomputer mdustry.

• The Z80 microprocessor; and associated family of peripheral controllers are linked by a vectored interrupt system. This system

",,-j

CONTROL

ONj

CONTROL

CPU { BUS CONTROL

M1

..

A,

MREQ A,

lORa A,

RD _WR

..

.,

A,

RFSH A,

.,

HAl.T A,

A"

zao CPU A12 A"

A"

Figure 1. Pin Functions

ADDRESS BUS

) DATA BUS

18400

Z80® CPU Central Processing Unit Product

Specification

March 1981

may be daisy-chained to allow implementation of a priority mterrupt scheme. Little, if any, additional logic is required for daisy-chaining.

• Duplicate sets of both general-purpose and flag registers are prOVided, easing the deslgn and operahon of system software through single-context sWltching, background-foreground programmmg, and Single-level interrupt processing. In addl- tion, two 16-blt index registers facilitate program processing of tables and arrays.

• There are three modes of high speed interrupt processmg: 8080 compatible, non-Z80 peripheral device, and Z80 Family penpheral wlth or without dalsy chain.

• On-chip dynamic memory refresh counter.

A11 A"

A12 A,

A" A,

eLK A,

0,

..

0, A,

+5 V _0,

..

GND

0, RFSH

Do M1

0, RESET

iNT BUSREC

NMI WAIT

HALT BUSACK

MREQ ViR

lORa AD

Figure 2. Pin Assignments

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General Description

The Z80, Z80A, and Z80B CPUs are third- generahon single-chip microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and third-generation mICroprocessors. The internal registers contam 208 bits of read/write memory that are accessible to the programmer.

These registers include two sets of six general- purpose registers which may be used individually as either 8-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers. A group of "Exchange" mstructions makes either set of main or alternate registers accessible to the programmer. The alternate set allows operation in foreground-background mode or it may

+5V -...

GND ....

CLOCK ....

be reserved for very fast interrupt response.

The Z80 also contams a Stack Pointer, Pro- gram Counter, two index registers, a Refresh register (counter), and an Interrupt register.

The CPU is easy to incorporate into a system smce it reqUires only a smgle + 5 V power source, all output signals are fully decoded and hmed to control standard memory or penpheral cirCUits, and is supported by an extensive family of peripheral controllers. The internal block diagram (Figure 3) shows the pnmary functions of the Z80 processors.

Subsequent text provides more detail on the Z80 1/0 controller family, registers, instruchon set, interrupts and daisy chaining, and CPU timing.

Figure 3. Z80 CPU Block Diagram

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ZBO Micro- processor Family

ZBO CPU Registers

2001-0213

The Zilog Z80 microprocessor is the central element of a comprehensive microprocessor product family. This family works together in most applications with minimum requirements for additional logic, facilitating the design of efficient and cost-effective microcomputer- based systems.

Zilog has desIgned five components to pro- vide extensive support for the Z80 microprocessor. These are:

• The PIO (Parallel Input/Output) operates in both data-byte I/O transfer mode (with handshaking) and in bit mode (without handshaking). The PIO may be configured to interface with standard parallel peripheral devices such as printers, tape punches, and keyboards.

• The CTC (Counter/Timer Circuit) features four programmable 8-bit counter/timers, Figure 4 shows three groups of registers within the Z80 CPU. The first group consists of duplicate sets of 8-bit registers: a principal set and an alternate set (designated by , [prime], e.g., A'). Both sets consist of the Accumula- tor Register, the Flag Register, and six general-purpose registers. Transfer of data between these duplicate sets of registers is accomplished by use of "Exchange" instructions. The result is faster response to interrupts and easy, efficient implementation of such versatile programming techniques as background-

MAIN REGISTER SET

A 'ACCUMULATOR F FLAG REGISTER

B GENERAL PURPOSE C GENERAL PURPOSE

D GENERAL PURPOSE E GENERAL PURPOSE

H GENERAL PURPOSE L GENERAL PURPOSE

- 4 - - - -8 BITS _

_ - - - 1 6 8 I T 5 - - - _ +

IX INDEX REGISTER

IV INDEX REGISTER

SP STACK POINTER

PC PROGRAM COUNTER

I INTERRUPT VECTOR

I

R MEMORY REFRESH A'

B'

D'

H'

each of which has an 8-bit prescaler. Each of the four channels may be configured to operate in either counter or timer mode.

• The DMA (Direct Memory Access) controller provides dual port data transfer operations and the ability to terminate data transfer as a result of a pattern match.

• The SIO (Serial Input/Output) controller offers two channels. It is capable of operating in a variety of programmable modes for both synchronous and asynchronous communication, including Bi-Synch and SDLC.

• The DART (Dual Asynchronous Receiver/

Transmitter) device provides low cost asynchronous serial communication. It has two channels and a full modem control interface.

foreground data processing. The second set of registers consists of six registers with assigned functions. These are the I (Interrupt Register), the R (Refresh RegIster), the IX and IY (Index Registers), the SP (Stack Pointer), and the PC (Program Counter). The third group consists of two interrupt status flip-flops, plus an additional pair of flip-flops which assists in identi- fying the interrupt mode at any particular time. Table I provides further information on these registers.

ALTERNATE REGISTER SET

ACCUMULATOR F' FLAG REGISTER

GENERAL PURPOSE c· GENERAL PURPOSE GENERAL PURPOSE E' GENERAL PURPOSE

GENERAL PURPOSE L' GENERAL PURPOSE

INTERRUPT FLIP FLOPS STATUS

c:J G

~

INTERRUPTS DISABLED STORES IFF1

4 ^~ :

INTERRUPTS ENABLED DURING NMI SERVICE INTERRUPT MODE FLIP FLOPS

lMFa IMFb

INTERRUPT MODE 0 NOT USED INTERRUPT MODE 1 INTERRUPT MODE 2

Figure 4. CPU Registers

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zaD CPU Registers (Continued)

Interrupts:

General Operation

Register

A, A' Accumulator F, F' Flags

B, B' General Purpose

C, C' General Purpose D, D' General Purpose

E, E' General Purpose

H, H' General Purpose L, L' General Purpose

Interrupt Register R Refresh RegIster

IX Index RegIster

IY Index RegIster

SP Stack Pomter

PC Program Counter

IFFI-IFF2 Interrupt Enable IMFa-IMFb Interrupt Mode

Size (Bits)

8 8 8 8 8 8 8 8

8 8

16 16 16 16 Fhp-Flops Fhp-Flops

Remarks

Stores an 'operand or the results of an operation.

See Instruction Set.

Can be used separately or as a 16-bit register with C.

See B, above.

Can be used separately or as a 16-bit register with E.

See D, above.

Can be used separately or as a 16-blt register with L.

See H, above.

Note: The (B,C), (D,E), and (H,L) sets are combined as follows:

B - HIgh byte C - Low byte D - High byte E - Low byte H - High byte L - Lo,w byte

Stores upper eight bits of memory address for vectored interrupt processing.

PrOVIdes user-transparent dynamic memory refresh. Automabcally incremented and placed on the address bus during each instruction fetch cycle.

Used for indexed addressing.

Same as IX, above.

Stores addresses or data temporanly. See Push or Pop in instruc- tion set.

Holds address of next instrucbon.

Set or reset to mdicate interrupt status (see Figure 4).

Rellect Interrupt mode (see Figure 4).

Table 1.

zeo

CPU Registers

The CPU accepts two interrupt input signals: • Mode 1 - Peripheral Interrupt service, for use with non-g080/Z80 systems.

NMI and INT. The NMI is a non-maskable interrupt and has the highest priority. INT is a lower priority interrupt since it requires that interrupts be enabled in software in order to operate. Either NMI or INT can be connected to mulhple peripheral devices in a wired-OR configuration.

The Z80 has a single response mode for interrupt service for the non-maskable interrupt. The maskable interrupt, INT, has three programmable response modes available.

These are:

• Mode

a -

compatible with the 8080 microprocessor.

• Mode 2 - a vectored interrupt scheme, usually daisy-chained, for use with Z80 Family and compatible peripheral devices.

The CPU services interrupts by sampling the NMI and INT signals at the rising edge of the last clock of an instruction. Further interrupt service processing depends upon the type of mterrupt that was detected. Details on interrupt responses are shown in the CPU Timing Section.

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Interrupts:

General Operation (Continued)

Non-Maskable Interrupt (NMI). The non- maskable interrupt cannot be disabled by program control and therefore will be accepted at at all times by the CPU. NMI is usually reserved for servicmg only the highest Priority type interrupts, such as that for orderly shut- down after power failure has been detected.

After recogmtion of the NMI signal (providing BUSREQ is not active), the CPU jumps to restart location 0066H. Normally, software starting at thIS address contains the mterrupt service routine.

Maskable Interrupt (lNT). Regardless of the interrupt mode set by the user, the 280 response to a maskable mterrupt Input follows a common timing cycle. After the interrupt has been detected by the CPU (provided that interrupts are enabled and BUSREQ is not active) a special interrupt processing cycle begins. This is a special fetch (MI) cycle in which IORQ becomes active rather than MREQ, as in a normal MI cycle. In addition, thiS special MI cycle IS automatically extended by two WAIT states, to allow for the time required to acknowledge the interrupt request and to place the Interrupt vector on the bus.

Mode 0 Interrupt Operation. This mode IS compatible with the 8080 microprocessor mterrupt service procedures. The mterrupting device places an instruction on the data bus, which IS then acted on SIX times by the CPU.

This IS normally a Restart InstructlOn, whICh Will initiate an unconditional jump to the selected one of eight restart 10catlOns in page zero of memory.

Mode 1 Interrupt Operation. Mode I operation is very similar to that for the NMI. The prinCipal difference IS that the Mode I mterrupt has a vector address of 0038H only.

Mode 2 Interrupt Operation. ThiS mterrupt mode has been designed to utlhze most effec- tively the capabillhes of the 280 microprocessor and ItS assOCiated peripheral family. The Interrupting peripheral device ,selects the startmg address of the mterrupt service routme. It does thiS by placing an 8-blt address vector on the data bus durmg the mterrupt acknowledge cycle. The high-order byte of the mterrupt servICe routine address IS supphed by the I (Interrupt) regISter. ThIS flex- Ibility In selectmg the Interrupt servICe routine address allows the peripheral deVICe to use several different types of servICe routines.

These routines may be located at any available

location in memory. Since the interrupting device supplies the low-order byte of the 2-byte vector, bit 0 (Ao) must be a zero . . Interrupt Priority (Daisy Chaining and Nested Interrupts). The interrupt priority of each peripheral device is determined by its physical location within a daisy-chain configuration. Each device in the chain has an interrupt enable input line (lEI) and an interrupt enable output line (lEO), which is ·fed to the next lower priOrity deVICe. The first device in the daisy chain has its lEI input hardwared to a High level. The first device has highest priority, while each succeeding device has a corresponding lower priority. This arrange- ment permits the CPU to select the highest priority interrupt from several Simultaneously interrupting peripherals.

The interrupting device disables its lEO line to the next lower priOrity peripheral until it has been serviced. After serviCing, ItS lEO Ime is raised, allowing lower pnority peripherals to demand interrupt servicing.

The 280 CPU Will nest (queue) any pending interrupts or interrupts received while a selected peripheral is being serviced.

Interrupt Enable/Disable Operation. Two flip-flops, IFFI and IFF2, referred to in the register description are used to signal the CPU Interrupt status. Operation of the two flip-flops is described in Table 2. For more details, refer to the Z80 CPU Technical Manual and Z80 Assembly Language Manual.

Action IFFI IFF2 Comments

CPU Reset 0 0 Maskable mterrupt

!NT dIsabled

Dr InstructIon 0 0 Maskable mterrupt

executIon INT dIsabled

EI instructIon Maskable mterrupt

execution INT enabled

LD A,I mstructlon IFF2 - Panty flag execution

LD A,R mstructlon IFF2 - Panty flag executIon

Accept NMI 0 IFF] IFF] - IFF2

(Maskable mterrupt INT dIsabled) RETN mstructIon IFF2 IFF2 - IFF] at

execution complehon of an

NMI servIce routme.

Table 2. Siale 01 Flip-Flops

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Instruction Set

8-Bit Load Group

The 280 microprocessor has one of the most powerful and versatile instruction sets available in any 8-bit microprocessor. It includes such unique operations as a block move for fast, efficient data transfers within memory or between memory and 1/0. It also allows operations on any bit in any location in memory.

The following is a summary of the 280 instruction set and shows the assembly language mnemonic, the operation, the flag status, and gives comments on each instruction. The Z80 CPU Technical Manual (03-0029-01) and Assembly Language Programming Manual (03-0002-01) contain significantly more details for programming use.

The instructions are divided into the following categories:

o

8-bit loads

o

16-bit loads

o

Exchanges, block transfers, and searches o 8-bit arithmetic and logic operations

o

General-purpose arithmetic and CPU control

Symbolic Flags

Mnemonic Operation H P/V

LD r, r' r - r' X X

LD r, n X X

LD" (HL) , - (HL) X X

LD" (IX+d) r - (IX+d) X X

LD '. (IY+d) , - (IY+d) X X

LD(HL), , (HL) - , x X

LD (IX+d). , (JX+d) - r X X

LD (IY +d), , (IY+d) - , x X

LD (HL). n (HL) - n X X

·

LD (IX+d), n (IX+d) - n X X

LD (IY +d), n (IY+d) - n X

.

^X

LD A, (BC) A - (BC) X X

LD A, (DE) A - (DE) X X

LD A, (nn) A - (nn)

.

^X ^X

LD (BC), A (BC) - A X X

LD (DE), A (DE) - A X X

·

LD {nnl. A (nn) - A X X

LDA, I A- I X X IFF

LDA, R A-R X X IFF

LDI,A I - A X X

·

LDR, A R-A X

.

^X

NOTES r, r' means any of the regIsters A, B, C, D, E, H, L IFF the content althe mterrupt enable flip-flop, (IFF) IS

copLed mlo the P/V flag

For an expianatlOn of Ilag notatIOn and symbols lor

N C

o

16-bit arithmetic operations

o

Rotates and shifts

o

Bit set, reset, and test operations

o

Jumps

o

Calls, returns, and restarts o Input and output operations

A variety of addressing modes are implemented to permit efficient and fast data transfer between various registers, memory locations, and input/output devices. These addressing modes include:

o

Immediate

o

Immediate extended

o

Modified page zero

o

Relative 0 Extended

o

Indexed 0 Register 0 Register indirect

o

Implied

o

Bit

Opcod. No.of No.of M No.of T

76 543 210 Hox Byt •• Cycles Stale. Comments

01

,

_" _~

00 , 110 000 B

- n - 001 C

01 , lID 7 010 D

II OIl WI DD 19 011 E

01 , 101 100 H

- d - 101 L

II III 101 FD 19 III A

01 , lID - d -

Ol lID , 7

II 011 101 DD 19

01 110 ,

- d -

II III 101 FD 19

01 llO ,

- d -

OD lID 110 36 10

- n -

II 011 101 DD 19

00110110 36 - d - - n -

Il III 101 FD 19

00110 110 36 - d - - n -

OD 001 010 OA 7

00 011 010 IA 7

00 III 010 3A 13

- n -

OD 000 010 02 7

00 010 010 12 7

00 110 010 32 13

- n - II 101 101 ED 01 010 III 57 II 101 101 ED 01 OIl III 5F II 101 101 ED 01000 III 47 II 101 101 ED 01001 III 4F

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IS-Bit Load Symbolic Flags Opcoda Ho.of No.ol M Ho.ol T

Group ^Mnemonic ^Operation ⁵ ^Z ^H ^{P/V N} ^C 76 543 21D Hex Byt •• Cycl •• Stal •• Commont.

LO dd, nn dd - nn X X 00 ddO 001 10 dd Pair

QOllC-

- n - 01 DE

LD IX, nn IX - nn X X 11 011 101 DD 14 10 HL

00 100 001 21 11 SP

LD lY, nn lY - nn X

·

^X

^·

00 100 001 21 ¹¹^III^{101 FD} ¹⁴ - n -

LD HL, Inn) H - (nn+1) X X 00 101 010 2A 16

L - (nn)

LD dd, (nn) ddH - (nn+l) X X 11 101 101 ED 20

ddL - Inn) 01 ddl 011

- n -

LD IX, Inn) IXH - (00+ I) X

·

^X 11011 101 DD 20

IXL - Inn) 00 101 010 2A

LD IY, Inn) IYH - (no+ 1) X X

·

11 III 101 FD 20

IYL - Inn) 00 101 010 2A

- n -

LD Inn), HL (no+l) - H X X 00 100 010 22 16 N

(nn) - L 00

C

LD Inn), dd (nn+ 1) - ddH X II 101 101 ED 20 t"l

(nn) - ddL 01 ddO 011 IV

- n - c:::I

LD Inn), IX Inn+ I) - IXH X

·

11 Oil 101 DD 20

Inn) - IXL 00 100 010 22

- n -

LD (nn), IY (nn+ 1) - IYH X

·

^X II 111 101 FD 20

(nn) - IYL 00 100 010 22

- n -

LD SP, HL SP - HL X X 11 III 001 F9 6

LD SP, IX SP - IX X X 11 Oil 101 DD 10

11 III 001 F9

LD SP, IY SP - IY X

·

^X

·

11 I II 101 FD 10

11 III 001 F9 ~

PUSH qq ISP-2) - qqL X

·

^X II qqO 101 II 00 BC

ISP- I) - qqH 01 DE

SP-SP-2 10 HL

PUSH IX ISP-2) - IXL X X 1I OIl 101 DD IS 11 AF

ISP- I) - IXH 11 100 101 E5

SP-SP-2

PUSH IY ISP-2) - IYL X X 11 III 101 FD IS

(SP-I) - IYH 11 100 101 E5

SP-SP-2

POPqq qqH - ISP+ I) X X 11 qqD 001 10

qqL - ISP) SP-SP+2

POP IX IXH - ISP+ I) X X 11 Oil 101 DD 14

IXL - (SP) 11 100 001 EI

SP-SP+2

FOPIY IYH - (SP+ I) X X 11 III 101 FD 14

IYL - (SP) 11 100 001 EI

SP-SP+2

NOTES dd IS any of the register pdlrs BC, DE, HL, SP.

qq IS any of the regIster pcHrS AF, BC. DE, HL

(PAIR1H. (PAIR1L refer to high order and low order eight bits of the register pel1r respecllvely, e g, BeL"" C, AFH "" A

Exchange. EX DE, HL DE - HL X X II 101 Oil EB

Block EX AF, AF' AF - AF' X X 00 001 000 08

EXX BC - BC' X X II Oil 001 D9 Reglster bank and

Transfer. ^{DE - DE'} auxlhary register

Block Search ^{HL - HL'} bank exchange

EX (SP), HL H-ISP+I) X X II 100 Oil E3 19

Groups ^{L - ISP)}

EX (SP), IX IXH - ISP+ I)

.

^X ^X 11 011 101 DD 23

IXL - ISP) II 100 Oil E3

EX ISP), IY IYH - ISP+ I) X X 11 111 101 FD 23

IYL - (SP)

<D 11 100 Oil E3

LDI (DE) - IHL) X X 11 101 101 ED 16 Load (HL) mto

DE - DE+ I 10 100 000 AD (DE), mcrement

HL - HL+I the pomters and

BC - BC-I decrement the byte

counter (Be)

LDIR IDE) - IHL) X 0 X 0 II 101 101 ED 21 JlBC ,,0

DE - DE+ I 10 110 000 BO 16 II BC ~O

HL - HL+I BC - BC-I Repeat untll BC ~ 0

NOTE CI)P/V flag IS 0 d the result 01 BC-J '" 0, otherwLse PlY = I

2001-001 11

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Exchange. Symbolic Flags Opcode No.of No.of M No.of T

Block ^Mnemonic ^Operation ⁵ ^Z ^H ^P/V^N ^C 76 543 210 Hex Bytas Cycles States Comments

Transfer. CD

Block Search ^LDD (DE) - (HL)

.

^x ⁰ ^X II lOi lOl ED 16

Groups DE - DE-I lO 101 000 A8

HL - HL-I

(Contmued) BC - BC-I

LDDR (DE) - (HL) X 0 X 0 II lOl lOl ED 21 !fBC '" 0

DE - DE-I lO III 000 B8 16 !f BC ~ 0

HL - HL-I BC - BC-I Repeat unlll BC ~ 0

@ CD

CPI A - (HL) X X II 101 lOl ED 16

HL - HL+l 10 lOO DOl Al

BC - BC-I

@ CD

CPlR A - (HL) X X 11 101 101 ED 21 IfBC*Oand

A", (HL)

HL - HL+ 1 10 llO DOl BI 16 If Be"" a or

BC - BC-I A = (HL)

Repeat unhl A = (HL) or BC ~ a

@ CD

CPO A - (HL) II lOi lOl ED 16

HL - HL-I 10 101 DOl A9

BC-BC-I

@ CD

CPDR A - (HL) II lOi lOl ED 21 lIBC*Oand

A", (HL)

HL - HL-I 10 III DOl B9 16 IfBC=Oar

BC - BCci A ~ (HL)

Repeal unlll A = (HL) or BC ~ 0

NOTES CD PJV flag IS 0 11 the re3ult 01 Be -I = 0, otherwlse PIV =-I G)ZlIagls lIlA ~ (HL). otherWIse Z :0 0

8-Bit ADDA. r A - A + r X X V lO IQ!l2J ' ~

Arithmetic ^{ADD A,}ⁿ Â-A+n ^X ^X ^V ÎIÎQQQ]^llO ^{000 B}

and Logical ^DOl_{010 D}^C

Group ADD A, (HL) A - A + (HL) X V 10 IQQQ] 110 all E

ADD A, (IX+d) A - A + (IX+d) X X V II OIl 101 DO 19 100 H

lO IQQQ] 110 WI L

-

^d

-

^{III A}

ADD A, (lY+d) A - A + (lY+d) X X V 0 II III lOi FD 19

lO IQQQ] llO

-

^d

-

ADCA,s A - A+s+CY X V [QQjJ S 15 any of r, n,

SUB s A - A~s X V IQl]] (HL), (lX+ d),

(1Y + d) as shown

SEC A, 5 A - A-s-CY X X V IQIj] for ADD Instruchon

AND s A - A l \ s X P [i]QJ The mdlcated blts

OR e A - A V 5 X []]j] replace the [QQQJ In

the ADD set above

XOR s A - A $ S X X

mm

CP, A-e X X V [j]

INC r r - r + 1 X X V 00 , [i]QJ

INC (HL) (HLI -(HL) + I X X V 00 lID [i]QJ II

INC (lX+d) (IX+d) - X X V 0 II OIl WI DD 23

(IX+d)+ I 00 lID [i]QJ

-

^d

-

INC (IY +d) (lY+d) - X X V 0 II III 101 FD 23

(1Y+d)+ I 00 llO [i]QJ

-

^d

-

DEC m m - m-l X X V

mm

^m¹⁵any of r, (HL),

(IX + d)' (lY +d) as shown for INC DEC same formal and states as INC Replace IIQQ] wllh

ITQ] In opcode

(21)

General- Symbolic Flags Opcoda No.of No.of M No.of T

Purpose ^Mnemonic ^Operation ^S ^Z ^H ^P/V^N ^C 76 543 210 Hex Bytes Cycles State. Commonts

Arithmetic ^DAA Converts acc. content X X 00 100 III 27 Declmal adjust

and mto packed BCD accumulator.

following add or

CPU Control subtract WIth packed BCD operands.

Groups CPL A-A X 00 101 III 2F Complement

accumulator (one's complement).

NEG A-O-A X X V II 101 101 ED Negate acc (two's

01 000 100 44 complement)

CCF CY - CY X X 00 III III 3F Complement carry

flag

SCF CY - I X X 00 110 III 37 Set carry flag.

NOP No operahon X X 00 000 000 00

HALT CPU halted X X 01 110 110 76

Ol_ EI _ IFF - 0 IFF - I X X X X II 110 011 F3 II III 011 FB

IMO Set mterrupt X X II 101 101 ED

mode 0 01 000 110 46

1M 1 Set mterrupt X X 11 101 101 ED

mode 1 01 010 110 56

1M2 Set Interrupt X 11 101 101 ED

mode 2 01 011 110 5E

NOTES IFF mdlCllles the mterrupt enable fhp flop

CY mcilcdles the carry fhp flop !!oil

• mdlcdles interrupts <He not sampled at the end of EI or DI 00

C

IS-Bit ADD HL, S5 HL - HL+ss X X X 00 5sI 001 11 ~ ('3

Arithmetic ^{00 BC} ."

ADC HL, 55 HL - HL+ss+CY X X X V 11 101 101 ED 15 01 DE

=

Group 01 5s1 010 10 HL

11 SP

SBC Hr.., 55 HL - HL-ss-CY X X X V 11 101 101 ED 15

01 ssG OlQ

ADD IX, pp IX - IX + pp X X 11 011 !Ol DD 15 pp Reg.

01 ppl DOl 00 BC

01 DE 10 IX 11 SP

ADD IY, rr 1Y - 1Y + rr X X X

.

11 III 101 FD 15 rr Reg

00 rrl 001 00 BC

01 DE 10 IY II SP

INC 5S ss - ss + 1 X X 00 ssO OIl 6

INC IX IX - IX + 1 X X 11 011 101 DD 10

00 100 all 23

INC IY 1Y - IY + 1 11 III 101 FD 10

00 100 all 23

DEC ss 5S - ss-1 X X 00 ssl OIl 6

DEC IX IX - IX-l X X 11 all 101 DD 10

00 101 all 2B

DEC IY IY - IY-I 11 III 101 FD 10

00 101 011 2B NOTES reqlster pairs Be. DE, HL. SP

register pairs BC, DE. IX. SP register pairs BC, DE, IV, SP

Rotate and

Shift Group ^RLCA ^@]~J ^a ^X 00 000 III 07 Rotate left clrcular accumulator, RLA l@j~ a X 00 010 III 17 Rolate left

accumulator

RRCA L~@] ^a ^X 00 001 III OF Rotate fight clrcular

accumulator

RRA ~@J ⁰ ^X 00 011 III IF Rotate fight

accumulator

RLe r X 0 X P 11 001 011 CB Rotate left Circular

00 000 c register r

RLC (HL) X a X P 11 001 011 CB 15 ~

000 B

00000110 001 C

RLC (IX +dl @]~J X 0 X P 11 011 101 DO 23 010 D

011 E

c,(HLI.(lX + dUlY + d) 11 001 011

-

^d

-

CB 101 100 H L

00 000 110 III A

RLC (lY +d) X a X P 11 III 101 FD 23

11 001 011 CB

- ^d

-

Instruchon format

l@j~ ^00000110 and states are as

RL m X a X P 010 shown for RLC's

m=r.(HLl.(IX + d),(IY + d) To form new

L~@] opcode replace

RRC ill X a x P 001 000 or RLC's

m:; r,(HL).(IX +d).(IY + d)

With shown code

2001,001 13

(22)

Rotate and Shift Group (Continued)

Bit Set. Reset and Test Group

Jump Group

Mnemonic

RR m

SLA m

SRA m

SRL m

RLD

RRD

BIT b, r BIT b, (HL)

Symbolic Operation

~@J

m!!! r,(HL),(IX + d).(IY + dJ

@]~o m= r,CHL),(IX + d),OY + dJ

~[ill

m"" r,(HL).(IX + d).(IY +d) o~@]

m= ,,(HL),(lX +d),(lY + d)

~~~

A (HLJ

17-413>1 171_~ol

A (HL)

Z - rb

Z - (HL)b BIT b, (IX+d)b Z - (IX+d)b

BIT b, (lY+d)b Z - (IY+d)b

SET b, r fb - I SET b, (HL) (HL)b - I SET b, (lX+d) (lX+d)b - 1

SET b, (lY + d) (lY + d)b - 1

RES b, m mb - 0

m &: T, (HL),

(lX+dl.

OY +d)

s z

I

x

X X

X

'Flags Opcode No.of No.of M No.of T

H P/V N C ,76 543 210 Hex Bytes Cycle,B Slates

X 0 X P

X 0 X

X X P 0

X X P

X 0 X P 0

X X X

X X X 0

X X X a

X X 0

x x x

X • X

X •

IQIj]

[jQQJ [jQj]

lITII

11 101 101 ED 01 101 III 6F

II 101 101 ED 01 100 III 67

11 001 011 CB 01 b 11 001 011 CB 01 b 110 II 011 101 DD II 001 011 CB

- d - 01 b 110 11 111 101 FD 11 001 011 CB

- d - 01 b 110

11 001 011 CB

IIlI b 11 001 011 CB

IIlI b 110 11 011 101 DO II 001 011 CB

- d -

IIlI b 110 11 III lOl FD 11 001 011 CB

- d -

IIlI b 110

llil

18

12 20

20

15 23

23

NOTES The notatIon mb mdlcates bIt b (0 10 7) or locdhon m

IP nn PC - nn X 11 000 all C3 10

IP cc, nn If condition cc IS X 11 010 10

true PC - nn, otherWise conhnue

JR e PC - PC+e X X 00 OIl 000 18 12

- 1?-2 -

IRC, e 11 C = 0, X 00 III 000 38

continue - e-2 -

11 C = 1, 12

PC - PC+e

JR NC, e 11 C = 1, X

.

00 110 000 30

contmue - e-2 -

11 C = 0, 12

PC - PC+e

IP Z, e 11 Z = 0 X 00 101 000 28

contmue - e-2 -

)f Z = I, 12

PC - PC+e

IR NZ, e )f Z = L X

.

^X 00 IDO 000 20

conhnue - e-2 -

)f Z = 0, 3 . 12

PC - PC+e

Comments

Rotate dlgll left and rlqht between the accumulator dnd locatIOn (HL) The content of the

upper half of the accumulator IS

unaffected

r Reg

~ 001 C 010 0 011 E 100 H 101 L III A b Bll Tested 000 0 001 1 010 2 011 3 100 101 lID III

To form new opcode replace

[ill of SET b, 5 WIth [QJ Flags and hme slales for SET lnstruchon

cc Condition

000 NZ n~

001 Z zero 010 NC non-carry 011 C carry 100 PO panty odd 101 PE panty even 110 P sign poslhve III M sign negahve If condlhon not met If condllion IS met.

If condltlOn not met If condlhon IS met If ,-ondltIon not met If condition ]S met If condlhon not met 11 condlhon IS met

Microcomputer Components Data Book

Microcomputer

Components

Data Book

Microcomputers in Every Form

Table of Contents

I

2

3

4

5

6

7

Table of Contents

zao

8

9

10

Z80 Family

Zilog ~

Zilog Z80® Family Faster Z80B

Peripheral Controllers

~ Zilog

",,-j

ONj

..

..

.,

.,

18400

Z80® CPU Central Processing Unit Product

Specification

..

..

I

c:J G

~

4 ~ :

zeo

a -

o

o

o

o

·

.

.

·

·

.

o

o

o

o

o

o

o

o

o

o

o

o

,

·

·

·

·

·

·

·

·

·

.

.

-

-

-

-

mm

-

4 ^~ :

^·