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Energy Efficient Techniques using FFT for Deep Convolutional Neural Networks

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Figure

Figure 1. Hardware architecture of radix-2 Single-path Delay Feedback (SDF) Decimation In Frequency (DIF) pipeline FFT.
Figure 3. Hardware architecture of 2D FFT.
Figure 4. Data flow example of the 2D MDF FFT.
Figure 6. Data flow for computing the convolution of M images K channels and F filters K channels.
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