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Physical Origin of the Gate Current Surge During Short-Circuit Operation of SiC MOSFET

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This is an author’s version published in:

http://oatao.univ-toulouse.fr/23888

To cite this version:

Boige, François and Trémouilles, David and Richardeau,

Frédéric Physical Origin of the Gate Current Surge During

Short-Circuit Operation of SiC MOSFET. (2019) IEEE

Electron Device Letters, 40 (5). 666-669. ISSN 0741-3106

Official URL:

https://doi:10.1109/LED.2019.28969397

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Physical Origin of the Gate Current Surge

During Short-Circuit Operation

of SiC MOSFET

F. Boige, D. Trémouilles, and F. R

i

chardeau

Abstract-

During the short circuit of a vertical 4H-SiC

power MOSFET, a high gate current starts to flow through

the gate dielectric. We demonstrate that the Schottky emis­

sion is the main physical mechanisms.

Index

Tenns

-4H-SiC MOSFET

,

short-circuit, gate oxide,

Schottky emission, Fowler-Nordheim.

1

.

INTRODUCTION

H

IGH performance electrical-power switches, offering the

lowest possible energy losses are required to manage

electricaJ power efficiently. Power devices based on wide

bandgap material like Silicon Carbide (SiC) MOSFET are

emerging as an effective technology solution to provide

such high performance switches. One main obstacle of the

SiC MOSFET expansion to industrial application is their

reliability and especially their low robustness compared with

Silicon devices in short-circuit (SC) operation [l]-[7]. The

observed behavior is different compared to Si devices. lndeed,

the SC current density is much higher and after few rnicrosec­

onds in SC operation, a large gate current appears. This current

has been studied from a "user point of view" in [2] and some

physical explanation have been proposed in [7] and [8]. It is

generally assumed that the physical origin of this gate current

is due to Fowler-Nordheim (F-N) tunneling. However, in SC

condition and especially with a SiC power device, the junction

temperature rises rapidly to reach 1200 K to 1 800 K [5], [9].

Furthermore, the gate electrical field is at nominal level

(� MY/cm) which does not favor F-N conduction which is

supposed to be triggered by a high electric field and is hardly

a fonction of the temperature.

In this work, we investigated on the physical conduction

mechanism which best corresponds with the experimental

behav

i

or on a vertical power device.

1200 1300 1400 1500 1600 Temperature (K.) (b)

Fig. 1. (a) Waveforms of a SiC 1200v 80

m.a

MOSFET SiC in short­ circuit operation for two v05. (RG = 47

.a,

Vgs = 20 V). (b) Gate current vs Temperature at RG = 47

.a,

Vbuffer = 20 V e0x = 50 nm S0x = 3.32 mm2.

In the first section, the experimentaJ results and the main

hypothesis are discussed. In the second section, the F-N mode!

and the therrnionic ernission mode! are presented and com­

pared. Finally, these models are discussed regarding experi­

mental observation.

Il. EXPERIMENTAL RESULTS

The device under test (DUT) is a 1200 V 80 mü

4H-SiC planar power MOSFET. The DUT was tested during

SC stress with increasing drain bias until device failure. The

experimentaJ setup is described in [10). The waveforms of the

SC tests are presented in

F

i

g

.

l a

. During the SC, the DUT

undergoes a high power-density peak leading to a fast rise

of its junction temperature. A ID thermal mode! bas been

developed in [9] in order to estimate this temperature. The

thermal mode! is composed of the top aluminum layer and

the SiC bulk. The heat dissipated during the short-circuit is

Jocated in the depletion layer just under the junction. Ail

the physical pararneters are temperature dependent.

In the

two tests presented in

F

i

g

.

l a

,

all gate currents approxi­

mately can rise up to 200

mA

and behave similarly versus

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(5)

[2] F. Boige and F. Richardeau, “Gate leakage-current analysis and mod-elling of planar and trench power SiC MOSFET devices in extreme short-circuit operation,” Microelectron. Rel., vols. 76–77, pp. 532–538, Sep. 2017. doi:10.1016/j.microrel.2017.06.084.

[3] R. Ouaida, M. Berthou, J. León, X. Perpiñá, S. Oge, P. Brosselard, and C. Joubert, “Gate oxide degradation of SiC MOSFET in switching conditions,” IEEE Electron Device Lett., vol. 35, no. 12, pp. 1284–1286, Dec. 2014.

[4] C. Chen, D. Labrousse, S. Lefebvre, M. Petit, C. Buttay, and H. Morel, “Study of short-circuit robustness of SiC MOSFETs, analy-sis of the failure modes and comparison with BJTs,”

Microelec-tron. Reliab., vol. 55, nos. 9–10, pp. 1708–1713, Aug./Sep. 2015.

doi:10.1016/j.microrel.2015.06.097.

[5] Z. Wang, X. Shi, L. M. Tolbert, F. Wang, Z. Liang, D. Costinett, and B. J. Blalock, “Temperature-dependent short-circuit capability of silicon carbide power MOSFETs,” IEEE Trans. Power Electron., vol. 31, no. 2, pp. 1555–1566, Feb. 2016.

[6] G. Romano, A. Fayyaz, M. Riccio, L. Maresca, G. Breglio, A. Castellazzi, and A. Irace, “A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs,” IEEE J. Emerg.

Sel. Topics Power Electron., vol. 4, no. 3, pp. 978–987, Sep. 2016.

doi:10.1109/JESTPE.2016.2563220.

[7] S. Mbarek, F. Fouquet, P. Dherbecourt, M. Masmoudi, and O. Latry, “Gate oxide degradation of SiC MOSFET under short-circuit aging tests,” Microelectron. Reliab., vol. 64, pp. 415–418, Sep. 2016. doi:10.1016/j.microrel.2016.07.132.

[8] T.-T. Nguyen, A. Ahmed, T. V. Thang, and J.-H. Park, “Gate oxide reliability issues of SiC MOSFETs under short-circuit opera-tion,” IEEE Trans. Power Electron., vol. 30, no. 5, pp. 2445–2455, May 2015.

[9] F. Boige, F. Richardeau, S. Lefebvre, and M. Cousineau, “SiC power MOSFET in short-circuit operation: Electro-thermal macro-modelling combining physical and numerical approaches with circuit-type imple-mentation,” Math. Comput. Simul., vol. 158, pp. 375–386, Apr. 2019. doi:10.1016/j.matcom.2018.09.020.

[10] F. Boige, F. Richardeau, S. Lefebvre, J.-M. Blaquiére, G. Guibaud, and A. Bourennane, “Ensure an original and safe ‘fail-to-open’ mode in planar and trench power SiC MOSFET devices in extreme short-circuit operation,” Microelectron. Reliab., vols. 88–90, pp. 598–603, Sep. 2018. doi:10.1016/j.microrel.2018.07.026.

[11] F.-C. Chiu, “A review on conduction mechanisms in dielectric films,” Adv. Mater. Sci. Eng., vol. 2014, 2014, Art. no. 578168. doi:10.1155/2014/578168.

[12] M. Nawaz, “On the evaluation of gate dielectrics for 4H-SiC based power MOSFETs,” Act. Passive Electron. Compon., vol. 2015, 2015, Art. no. 651527. doi:10.1155/2015/651527.

[13] G. Pananakakis, G. Ghibaudo, R. Kies, and C. Papadas, “Tempera-ture dependence of the Fowler⣓Nordheim current in metal-oxide-degenerate semiconductor structures,” J. Appl. Phys., vol. 78, no. 4, p. 2635, Jun. 1998. doi:10.1063/1.360124.

[14] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, no. 1, pp. 278–283,

Nov. 1969. doi:10.1063/1.1657043.

[15] D. Schroeder and A. Avellán, “Physical explanation of the barrier height temperature dependence in metal-oxide-semiconductor leakage current models,” Appl. Phys. Lett., vol. 82, no. 25, pp. 4510–4512, Jun. 2003. doi:10.1063/1.1587256.

[16] V. V. Afanas’ev, M. Bassler, G. Pensl, M. J. Schulz, and E. S. von Kamienski, “Band offsets and electronic structure of SiC/SiO2

interfaces,” J. Appl. Phys., vol. 79, no. 6, pp. 3108–3114, Mar. 1996. doi:10.1063/1.361254.

[17] F. Boige, F. Richardeau, D. Trémouilles, S. Lefebvre, and G. Guibaud, “Investigation on damaged planar-oxide of 1200 V SiC power MOSFETs in non-destructive short-circuit operation,”

Microelectron. Reliab., vols. 76–77, pp. 500–506, Sep. 2017. doi:10.1016/j.microrel.2017.06.085.

[18] N. Hansen, “A CMA-ES for mixed-integer nonlinear optimization,” INRIA, Villers-lès-Nancy, France, Res. Rep. RR-7751, Oct. 2011.

[19] RefractiveIndex. INFO—Refractive Index Database. Accessed: Oct. 26, 2018. [Online]. Available: https://refractiveindex.info/

Figure

Fig .  1.  (a)  Waveforms of  a SiC  1200v 80  m.a  MOSFET SiC  in short­ circuit operation for two  v05

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