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WRITE PROTECT OPTION COMMANDS (SP, CP)

Dans le document TEXAS INSTRUMENTS (Page 118-122)

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9.6.13 WRITE PROTECT OPTION COMMANDS (SP, CP)

These commands allow control of the optional hardware memory write protect feature on 990/4 computers. These commands are ignored on a 990/5 computer.

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9.6.13.1 Set Write Protect Region (SP). The Set Write Protect Region command sets the write protect region to the address specified in the command. This command is only valid if the user has a 990/4 computer with the write protect option. A protection violation generates a general inter-rupt signal which may be wired to any available interinter-rupt level. Refer to the Model 990/4 Computer Computer System Hardware Reference Manual for the procedure for wiring a memory board to a desired interrupt level.

To set a write protect region, the lower and upper bounds musf be output to CRU base address I FA016 . The most significant bit (bit 0) is the Protect/Permit bit. Bit 0, when set to I, indicates write permit, and, when set to 0, indicates write protect. To specify the protect region, memory is divided into 256-word blocks. The lower and upper bounds are each seven bits long and serve as an index into the memory addresses to specify which contiguous 256-word block of memory is to be protected. For example, the lower bound of the protect region equal to 200016 would be represented in the Protect register as 1016 , The memory block beginning at location 200016 is the sixteenth 256-word (512-byte) memory block. A bound is calculated by dividing the starting ad-dress of the memory block by 20016 (51210 ), In this example, 200016 divided by 20016 is equal to 1016 , The upper bound is not included in the protect region. When outputting to the CRU Protect register to specify the protect bounds, a Load CRU (LDCR) instruction with a count of 16 must be used to set all 16 bits because the Protect register works like a shift register. To protect the memory range 200016 to 400016 , the lower bound is set equal to 1016 , the upper bound is set to 2016 , and the Protect bit is set to O. Therefore, the Protect register is set to 102-016 by out-puttin'g these fields to the CRU in the format specified in figure 9-1A.

(A) 13337 3

0 1 7 8 9 15

H

LB

~

UB

NOT USED BIT FIELDS

P PROTECT/PERMIT BIT O-PROTECT

1-PERMIT LB LOWER BOUND UB UPPER BOUND

NOTES

THE CRU OUTPUT DATA FORMAT IS THE SAME AS THE FORMAT OF DATA IN MEMORY BEFORE IN LDCR INSTRUCTION IS EXECUTED.

BIT5 1 AND 9 ARE THF.: MOST SIGNIFICANT BITS. AND BITS 7 AND 15' ARE THE LEAST SIGNIFIC.ll,.NT BITS OF THE LB AND UB FIELDS.

Figure 9-1A. CRU Outp-utData Fonnat

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When an attempt is made to write into a memory location within the protected region, the Protect Violation flag is set to FFFF 16. This flag, which is normally 0, can be sensed by reading any of the 16 CRU bits at base IFA016 • If this protected region is within the TMS9900 on-board RAM, the write is not inhibited. If this protect region is on the expansion memory card, the write is inhibited.

The Protect Violation flag may be cleared in two different ways:

1. I/O RESET (RSET) - This machine instruction clears the violation flag and sets bit 0 of the Protect register to 1 (not protected).

2. Output a 1 to any or all of the 16 bits of the Protect register.

If the user has wired his system such that a write protection violation causes an interrupt at a . certain level, he must initialize the trap vector for that level and process the interrupt. The level 2 trap vector is initialized automatically by the Debug Monitor. The user may take advantage of this fact and wire his memory board interrupt to level 2. The system then prints:

**MX06**

when a protection violation occurs. When this happens, a RSET instruction is executed and the user must reestablish the protect bounds before starting execution again.

Syntax definition:

SP {b' ... } <lower mem addr> {b' ... } <upper mem addr>

• The command is terminated by a carriage return.

When the user issues an SP 0600,0800 and then an EX command, his program begins execution.

Should the user program then attempt to write into memory location 0700, hardware write protect sets the protection violation flag in the CRU and interrupts the CPU if the user has wired that interrupt.

Parameters:

lower mem addr Lower boundary memory address of the protected region. Required parameter. Hexadecimal

number.

upper mem addr Upper boundary memory address of the protected region. Required parameter. Hexadecimal

number.

Description: This command sets the write protect region from the lower to the upper memory bound addresses. If the memory addresses entered are not on 256-word boundaries, the bounds·

will be set at the next lower 256-word boundary. The lower bound is included within the protect region but the upper bound is not.

The SP command overrides any previously defined protect region.

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~---When the upper and lower bounds are sent to the CRU, the Protect Violation flag is cleared if it has been set.

Error message:

MS05 Parameter specification error. Either a required parameter is missing, or the lower bound is greater than or equal to the upper bound.

Application note: This command is ignored if the write protect option is not implemented in the system hardware.

Examples:

.SP 1000,2000

This command protects a region in memory from 100016 to 1 FFF 16 • . SP 1000,1 Faa

This command protects a region from 100016 to IDFF16 • The address IF0016 is not a 256-word boundary; therefore, the upper bound is set at the next lower 256-word boundary, 1EOO.

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946258-9701 9.6.13.2 Clear Write Protect Region (CP). The Clear Write Protect Region command clears the

protect register and removes protection from the write-protected region. ( Syntax definition:

CP

The command is terminated by a carriage return.

Description: The CP command clears the Protect register and sets the Protect/Permit bit to Permit.

The Protect Violation flag is cleared if it has been set.

Application note: This command is ignored if the write protect option is not implemented in the system hardware.

Example:

.CP

Dans le document TEXAS INSTRUMENTS (Page 118-122)