3 VME SLAVE INTERFACE
3.2 VME Access to the local MAIN MEMORY
The gate array supports accesses from the VMEbus to the local MAIN memory by providing address decoding and Address Modifier decoding, both software selectable.
Accesses from the VME bus to the local main memory are decoded in the 32 bit address space of the VMEbus. The 4 Gbyte total address space is decoded into 16 pages each of 256 Mbyte. The page can be defined by the VMEPAGE register, whose register bits are compared with the VME address lines A31..A28.
The VMEPAGE is then further decoded into intervals. This is performed by two address comparators, one decoding a bottom page and the other decoding a top page.
The bottom page decoder accomplishes a higher-or-equal comparison and the top page decoder a lower-or-equal comparison of the applied VME address.
The VME address is valid when both comparisons are valid.
The address interval, in which a VMEbus access is decoded, ranges from the lowest (bottom) page to the highest (top) addressable page.
The address comparators evaluate the VME address lines A27..A12 for the interval decoding.
The remaining address lines A11..A00 are not decoded, which allows the interval size to be selected in steps of 4KByte.
An interval contains the address range that starts with the base address of the bottom page and finishes with the end address of the top page.
Accesses from the VMEbus to the local MAIN memory have to be executed with a valid Address Modifier Code. Four AM codes can be selected in the ENAMCODE register.
Selecting one of the Address Modifier codes enables the decoding range.
Additionally, the gate array provides write protection for the decoding interval. The access qualification is available for each selected AM code separately.
3.2.1 Decoding scheme for accesses to the local MAIN memory from the VMEbus side
VME Page Decoding:
VME Address line A31 A30 A29 A28
- - - - P31 P30 P29 P28 VMEPAGE Register Bits
Address Interval Decoding:
VME Address line
A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
T27 T26 T25 T24 T23 T22 T21 T20 T19 T18 T17 T16 T15 T14 T13 T12
TOPPAGEU TOPPAGEL
B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12
BOTTOMPAGEU BOTTOMPAGEL
3.2.2 VME Page Decoding
The access page to the local MAIN memory from VMEbus side is a 256 MByte page, specified by the VMEPAGE register of the gate array.
The four register bits P31..P28 are compared with the VME address lines A31..A28, in this order. They define the highest nibble of the 32 bit VMEbus access address.
3.2.2.1 Register VMEPAGE
Register Mnemonic Address R/W Default
VME PAGE register VMEPAGE $FFD00200 R/W $00
Format of VMEPAGE
7 6 5 4 3 2 1 0
- - - - P31 P30 P29 P28
3..0 P[31..28] - This bitfield selects the page in
which the local main ram can be accessed from the VME side.
3.2.3 VME Interval Decoding
The following registers define the decoding interval for VME accesses to the local MAIN memory.
3.2.3.1 Registers for Bottom and Top page selection
Register Mnemonic Address R/W Default
Bottom Page Register U BOTTOMPAGEU $FFD002D0 R/W $00 Bottom Page Register L BOTTOMPAGEL $FFD002D4 R/W $00 Top Page Register U TOPPAGEU $FFD002D8 R/W $00 Top Page Register L TOPPAGEL $FFD002DC R/W $00
The interval decoding of the access range is accomplished by two page decoders. One page decoder selects the BOTTOM page and the other the TOP page of the address interval.
Between these pages all VME addresses are valid.
Each page decoder compares 16 address lines (A27..A11) of the VMEbus with the contents of two 8-bit registers.
The bottom page decoder compares the address lines A27..A20 with the BOTTOMPAGEU register and the address lines A19..A12 with the BOTTOMPAGEL register.
Likewise, the top page decoder compares the VME address lines A27..A20 and A19..A12 with the registers TOPPAGEU and TOPPAGEL respectively.
Each register set (bottom or top) specifies the base address of its respective 4 KByte page.
The register contents of the top page do not define the end address of an interval, but specify the base address of its top page.
The address interval, selected by these registers, ranges from the base address of the bottom page to the end address of the top page.
Format of BOTTOMPAGEU
7 6 5 4 3 2 1 0
B27 B26 B25 B24 B23 B22 B21 B20
7..0 B[27..20] These bits are compared with the VMEbus address lines A27..A20 and select the upper portion of the bottom page address.
Format of BOTTOMPAGEL
7 6 5 4 3 2 1 0
B19 B18 B17 B16 B15 B14 B13 B12
7..0 B[19..12] These bits are compared with the VMEbus address lines A19..A12 and select the lower portion of the bottom page address.
Format of TOPPAGEU
7 6 5 4 3 2 1 0
T27 T26 T25 T24 T23 T22 T21 T20
7..0 T[27..20] These bits are compared with the VMEbus address lines A27..A20 and select the upper portion of the top page address.
Format of TOPPAGEL
7 6 5 4 3 2 1 0
T19 T18 T17 T16 T15 T14 T13 T12
7..0 B[27..20] These bits are compared with the VMEbus address lines A27..A20 and select the lower portion of the top page address.
3.2.4 Enable Address Modifier Decoding
The address modifier code, which the VME master has to broadcast for a valid access to the main memory, is selectable in the ENAMCODE register.
After reset, no access to the main memory from VME side is possible since the register is cleared and all address modifier code selections are disabled.
Additionally, the decoding area can be protected from write accesses by VMEbus masters.
3.2.4.1 Register ENAMCODE
Register Mnemonic Address R/W Default
Enable AM code Register ENAMCODE $FFD002B4 R/W $00
Format of ENAMCODE
7 6 5 4 3 2 1 0
XSP XSD XUP XUD
7..6 XSP - Extended Supervisor Program Access AM code
00 disabled
01 disabled
10 enabled for READ-Access
11 enabled for R/W -Access
5..4 XSD - Extended Supervisor Data Access AM code
00 disabled
01 disabled
10 enabled for READ-Access
11 enabled for R/W -Access
3..2 XUP - Extended User Program Access AM code
00 disabled
01 disabled
10 enabled for READ-Access
11 enabled for R/W -Access
1..0 XUD - Extended User Data Access AM code
00 disabled
01 disabled
10 enabled for READ-Access
11 enabled for R/W -Access