INTERRUPT ACKNOWLEDGE

The FGA-002 gate array decodes interrupt acknowledge cycles from the processor and responds to the cycle by presenting an interrupt vector on the data pins DCPU31-DCPU24. The vector which is presented to the processor may be supplied by the gate array internal interrupt logic or by the external interrupter.

External Vector response is supported for the VMEbus interrupts and for the local interrupts LOCAL4-LOCAL7.

The vector which is supplied by an external interrupter is transmitted by the gate array from the LOCAL I/O bus or the VMEbus to the CPU data bus.

VMEbus interrupts are supported as external vector responses.

The gate array requires the interrupt vector to be presented at the data pins DVME0-DVME7 of the gate array. After being read in, the vector is presented to the CPU data pins DCPU24-DCPU31.

2.2.1 Internal Vector Response

When the gate array responds to an interrupt acknowledge cycle with an Internal Vector, it places the vector number of the acknowledged interrupt channel on the CPU data pins

DCPU24 - DCPU29. To complete the 8 bit vector information, the two uppermost vector bits determining the Interrupt Vector Page are provided by the CTL3 register and are driven on the DCPU30 - DCPU31 pins.

The gate array supports interrupt acknowledge cycles with the internal vector number when the following interrupt channels are decoded:

INTERRUPT CHANNEL VECTOR NUMBER

Mailbox 0 $00

2.2.2 Local I/O Vector Response or Internal Vector Response

The LOCAL4 - LOCAL7 interrupts are supported by three different modes of response to an interrupt acknowledge cycle of the processor.

The modes are:

1. Response with Internal Vector Number 2. Response with External Interrupt Vector 3. No response

The modes are selected in the control register LOCALIACK.

The register also controls the timing of the access on the LOCAL I/O bus which fetches the vector from the interrupting device.

The contents of this register have to be programmed according to the external hardware configuration.

INTERRUPT CHANNEL VECTOR NUMBER

LOCAL4 $34 or from Local I/O bus

LOCAL5 $35 or from Local I/O bus

LOCAL6 $36 or from Local I/O bus

LOCAL7 $37 or from Local I/O bus

When internal vector response is selected, the associated vector number of the acknowledged interrupt channel is presented to the processor.

For external vector response, the gate array fetches the interrupt vector on the Local I/O bus and transmits it to the CPU data bus. In this case, the external device connected to the Local I/O data bus of the gate array has to provide the interrupt vector.

The third selection is that the gate array does not respond to the IACK cycle of the processor. This mode supports interrupting devices which are directly connected to the CPU data bus.

External interrupters connected to the LOCAL4 - LOCAL7 interrupt channels are supported by the gate array’s four acknowledge outputs LIACK 4-7, respectively. A LIACKx output will be asserted low when the processor acknowledges the corresponding LOCALx interrupt.

2.2.2.1 Local IACK control register LOCALIACK

The 8 bit control register LOCALIACK is assigned to the LOCAL 4-7 interrupts and selects the internal or external vector response mode for these interrupts.

Also selectable by the LOCALIACK control register is the access time to the LOCAL I/O bus in an interrupt acknowledge cycle when the external response mode is needed.

The register is grouped into four bit fields where each field stores a 2 bit code to control the vector response mode of one of the LOCAL 4-7 interrupts.

Register Mnemonic Address R/W Default

Local IACK Control Reg. LOCALIACK $FFD00334 R/W $00

Format of LOCALIACK

7 6 5 4 3 2 1 0

LOCAL7 LOCAL6 LOCAL5 LOCAL4

7..6 LOCAL7 This bit field controls the vector

response mode of the gate array for the LOCAL 7 interrupt.

5..4 LOCAL6 This bit field controls the vector

response mode of the gate array for the LOCAL 6 interrupt channel.

3..2 LOCAL5 This bit field controls the vector

response mode of the gate array for the LOCAL 5 interrupt.

1..0 LOCAL4 This bit field controls the vector

response mode of the gate array for the LOCAL 4 interrupt.

The 2 bit code stored in the LOCALIACK register for the control of the vector response mode of the LOCAL 4-7 interrupts has the following selections:

00 = The gate array answers with an internal vector.

The vector of the corresponding LOCAL interrupt is driven on the CPU data bus signals DCPU31..DCPU24.

The corresponding LIACKx pin will be asserted.

01 = During the processor’s IACK cycle the gate array does not intervene but merely asserts the corresponding LIACK pin as soon as possible.

10 = Upon IACK, the gate array responds to the CPU with an external vector. The corresponding LIACKx signal will be asserted and the interrupting device has to supply the interrupt vector. The vector is read on the local I/O bus and presented on the CPU data bus. The access time to the interrupting device on the local I/O bus is 1 us.

11 = Upon IACK, the gate array responds to the CPU with an external vector. The corresponding LIACKx pin will be asserted and the interrupting device has to supply the interrupt vector. The vector is read on the local I/O bus and presented on the CPU data bus. The access time to the interrupting device on the local I/O bus is 500ns.

2.2.3 VMEbus Vector Response

VMEbus interrupts are handled by the gate array with an external vector response.

If a VMEbus interrupt is serviced by the processor, the FGA-002 gate array awaits vector data delivered by the VMEbus interrupter on data pins DVME0-DVME7.

The vector will be read in and transmitted to the CPU data pins DCPU24-DCPU31.

INTERRUPT CHANNEL VECTOR NUMBER

VIRQ7* external from VME

VIRQ6* external from VME

VIRQ5* external from VME

VIRQ4* external from VME

VIRQ3* external from VME

VIRQ2* external from VME

VIRQ1* external from VME

2.2.4 EMPTY Vector Response

The gate array responds to the IACK cycle of the CPU by presenting an interrupt vector. This is normally the interrupt channel vector which is decoded by the gate array interrupt logic or the external vector supplied by the interrupting device.

In order to guarantee that the interrupt channel which is addressed by the processor in the IACK cycle is decoded successfully by the gate array, the interrupt source must hold the request stable in the asserted state.

Care has been taken with the design of the gate array interrupt circuitry to prevent the IACK cycle from being terminated with a timeout bus error if a decoding fault occurs.

However, if an interrupt source could not be decoded in an IACK cycle, the gate array always supplies the EMPTY interrupt vector to the processor.

The EMPTY interrupt vector is assigned to the EMPTY interrupt channel and carries the vector number $3F.

The EMPTY interrupt channel is a virtual channel which means that there is no interrupt source to trigger this interrupt.

Accordingly it does not own an interrupt control register or an interrupt status register.