THEORY OF OPERATION

The functional description contained in Chapter 1 gives a brief overview of the TM03 tape formatter.

The discussions contained in Paragraph 4.1 are still of a general nature but are more detailed than that contained in Chapter 1. The write data path and read data path are discussed separately as distinct operations. In addition, each of the eight commands that the TM03 can process is discussed separately as an operational sequence with a corresponding flowchart. Some redundancy exists among the de-scriptions of the operational sequences in order to keep each of the eight sequences separate.

Figure 4-1 and Tables 4-1 and 4-2 illustrate and define all the signals on the Massbus and the slave bus.

Refer to them throughout the discussions of Chapter 4.

4.1.1 Write Data Path

The write data path, shown in the TM03 block diagram (Figure 1-7), is discussed in this section in greater detail (Figure 4-2).

To write data on tape, the Massbus controller, after loading the tape control register and the frame count register, loads the write data function code into the control register, places data on the data bus, and asserts RUN H to the TM03. When the TM03 is ready to accept a data word, it asserts SCLK to the Massbus controller, which responds by asserting WCLK to the TM03.

Signal Data Bus

Data Lines [0(0: 17)]

Data Lines Parity (DPA)

Sync Clock (SCLK)

Write Clock (WCLK)

Table 4-1 Massbus Interface Signals Function

These bidirectional lines transmit 18 parallel data bits to or from the TM03.

This bidirectional line transmits the data parity bit (odd parity) to or from the TM03. Data parity is simultaneously transmitted with the bits on the data lines.

During a data write, this line transmits SCLK from the TM03 to request write data from the Massbus controller. During a data read, this line transmits SCLK to the Massbus controller to indicate that read data is present on the data lines.

During a data write, this line transmits WCLK from the Mass-bus controller to strobe write data into the TM03.

Table 4-1 TM03 Interface Signals (Cont)

This line transmits RUN from the Massbus controller to initiate data transfer execution.

Normally, this line transmits EBL from the TM03 at the end of each record. However, for certain abnormal conditions where it is necessary to terminate the transport operation immediately, EBL is transmitted prior to the end of the record.

This bidirectional line transmits EXC from the TM03 to in-dicate that an error has occurred during data transfer, In some systems, EXC H can also be transmitted over this line from the controller to abort an in-progress data transfer.

During a data transfer (read/write), this bidirectional line trans-mits OCC from the TM03 to indicate that a transport has con-trol of the data bus. Once asserted, this signal prevents any other transport from using the data bus.

These bidirectional lines transmit 16 parallel control or status bits to or from the TM03.

This bidirectionalIine transmits control lines parity (odd parity) to or from the TM03. Control parity is simultaneously trans-mitted with the bits on the control lines.

These three lines transmit a 3-bit binary code from the Massbus controller to select a particular TM03.

These five lines transmit a 5-bit binary code from the Massbus controller to select one of the ten TM03 registers.

This line transmits the CTOD signal from the Massbus con-troller to indicate in which direction data is to be transferred on the control lines. For a controller-to-drive transfer, the con-troller asserts CTOD. Conversely, for a drive-to-concon-troller transfer, the controller negates CTOD.

This line transmits DEM from the Massbus controller to in-itiate a control bus transfer (inin-itiate "handshake").

This line transmits TRA from the TM03 in response to DEM.

The assertion of TRA indicates that data is available on the control bus.

This line transmits ATTN from the TM03 to indicate that a nontransfer error or transport status change has occurred.

Table 4-1 TM03 Interface Signals (Cont) transIl,i~itted at system startup or whenever the Massbus con-troller issues an initialize command.

This iline transmits MASSFAIL L negated from the Massbus controller to indicate that the controller power supply is oper-ating properly. If the controller power supply fails, MASSFAIL L is asserted, thus initializing the TM03 logic as well as pre-venting it from accepting erroneous control bus information.

Table 4-2 Slave Bus Interface Signals Function.

These lines select one of eight possible transports for command execution.

These. are the four command lines which determine transport

ope~ation.

This signal initiates transport response to the four command lines.

This signal causes the transport to terminate motion. (Does not apply to rewind, which terminates independently.) . This signal enables the transport to gate out a coded motion delay preset onto the read lines.

This signal is asserted by the TM03 while the transport is getting up to speed or not moving tape. It is not asserted while the IDB is being written.

Signal

Table 4-2 Slave Bus Interface Signals (Cont) Function

This clock, generated in the transport, is present at all times when the transport is selected, loaded with tape, and on-line.

The frequency of CLOCK depends on the transport tape speed [144 kHz for 114.3 cm/second (45 in/second) slaves; 240 kHz for 190.5 cm/second (75 in/second) slaves; 400 kHz for 317.5 cm/second (125 in/second) slaves].

This clock is transmitted to the TM03 by a powered, selected, on-line transport loaded with tape when it is running at speed (ACCL not asserted). The frequency of WR T CLK is a function of the DEN lines and of the transport tape speed, and controls the write timing frequency.

Asserted by the TM03 prior to the REC pulse that writes the LRC character.

These nine lines transmit read data from the transport to the TM03. (They also transmit the motion delay preset.)

A read strobe pulse generated by the transport at the end of the skew delay in NRZI mode.

Not Used. Tied to +dc.

Asserted when the transport detects the beginning-of-tape marker.

Asserted when the transport detects the end-of-tape marker.

Asserted while the selected transport is performing a rewind op-eration.

Always negated by a selected transport.

Asserted by a selected, powered transport.

Asserted by a selected, powered transport which is loaded with tape.

Asserted by a selected transport to indicate that tape motion has stopped.

Table 4-2 Slave Bus Interface Signals (Cont)

Asserted while the transport is decelerating, until it has stopped.

Asserted by a transport when instructed to operate in PE mode.

Asserted by a transport when it comes on-line.

\ Asserted at the completion of a rewind and when the transport ':comes on-line. It is also pulsed when the transport goes off-line or when the transport power fails. This line may be asserted by any slave, selected or not. Cleared by INIT or DRV CLR PLS.

Asserted when the selected transport detects that the write en-able ring has been removed from the tape reel.

A maintenance function. When asserted in NRZI mode, skew delays are tightened; in PE mode, on-the-fly error correction is inhibited.

Specifies the type of slave transport as follows:

o

These 16 lines contain the BCD code of the last four digits of the serial number of the selected transport.

'When asserted by the TM03, DRV CLR PLS clears SLA and

DATA LINES PARITY

CONTROL CONTROLLER TO DRIVE

"CLOCK L

MASSBUS INTERFACE SLAVE BUS INTERFACE

Figure 4-1 TM03 In terface Signals

~ I

-.J

MASS ,BUS

CONTROLLER ^"':1 -:;.;:-;;.::-~_., PIO MASS BUS

• MAY ALSO BE M8915 EXCEPT FOR 125 IPS TRANSPORTS (TU77) WHICH MUST USE M8915-YA

•• M8934-YA WHEN USED WITH 75 IPS SLAVES tTU45)

TM03 TAPE FORMATTER

(M5903 or M5903=Y A) --,

r

MASS BUS RECEIVERS

II · . . '

! ^I I ^{W~~~ ~ W~;~E}

~--" ^{BUFFER MUX}

OR OR

INPUT DATA

MUX LATCHES

II I I

WRITE

II

• DATA

___ .J I l-'\.j

L~

Figure 4-2 Write Data Path (Sheet 1 of 2)

PARITY BIT WRITE

VERTICAL PARITY

GENERATOR • ( a

a-BITS

I I

, _ _ J I

-TAPE

CONTROl-I

'I

I I

CRCC

L_~:=-_J

OJ

I