System intercommunication is carried out through the UNIBUS.
A device will request the UNIBUS for one of two purposes:
To make a non·processor (NPR) transfer of data. (Direct Data Transfers such as DMA), or
To interrupt program execution and force the processor to branch to a service routine.
There· are two sources of interrupts, hardware and software.
2.6.1 Hardware Interrupt Requests
A hardware interrupt occurs when a device wishes to indicate to the program, or Central Processor, that a condition has occurred (such as transfer completed, end of tape, etc.). The interrupt can occur on any one of the four Bus Request levels and the processor responds to the interrupt through a service routine.
2.6.2 Program Interrupt Requests
Hardware interrupt servicing is often a two-level process. The first level is directly associated with the device's hardware interrupt and consists of retrieving the data. The second, is a software task that manipulates the raw information. The second process can be run at a lower priqrity than the first, because the PDP-ll/45 provides the user with the means of scheduling his software servicing through seven levels of Program Interrupt Requests. The Program Interrupt Request Register is located at address 777772. An interrupt is generated by the programmer setting a bit in the high order byte of this register.
The .reader is referred to Appendix D for more detailed information.
2.6.3 Priority Structure
When a device capable of becoming bus master requests use of the bus, handling of the request depends on the hierarchical position of that device in the priority structure.
The relative priority of the request is determined by the Processor's priority and the level at which the request is made.
The processor's priority is set under program control to one of eight levels using bits 7-5 in the processor Status Word. Bus requests are inhibited on the same or lower levels.
Bus requests from external devices can be made on anyone of the between instructions providing that they occur on higher levels than the processor's. Therefore an interrupt may only occur on a Bus Request Level and not on a Non Processor Request level.
Any number of devices can be connected to a specific BR or NPR line.
If two devices with the same priority request the bus, the device
Program Interrupt Requests take precedence over equivalent level Bus Requests.
PROCESSOR STATUS WORD
CPU PRIORITY
PROCESSOR STATUS WORD
=7===~--PI-R-7---NPR----~--r-.---~-. .
Figure 2-10 UNIBUS Priority Structure 2.6.4 Non-Processor Data Transfers any two peripherals without processor supervision. These Non·Processor transfers, called NPR level data transfers, are usually made for Direct
prog-In the PDP-ll/45 an NPR device can gain bus control in 3.5 microseconds or less (depending on the number of devices on the UNIBUS), and can transfer 16-bit words to memory at the same speed as the effective cycle time of the memory being addressed.
2.6.5 Using the Interrupts
Devices that gain bus control with one of the Bus Request Lines (BR 7·
BR 4), can take full advantage of the Central Processor by requesting an interrupt. In this way, the entire instruction set is available for manipulat·
ing data and status registers.
When a service routine is to be run, the current task being performed by the central processor is interrupted, and the device service routine is initiated. Once the request has been satisfied, the Processor returns to its former task. Interrupts may also be used to schedule program exe·
cution by using the Program Interrupt Request.
2.6.6 Interrupt Procedure
Interrupt handling is automatic in the PDp·llj45. No device polling is required to determine which service routine to execute. The operations required to service an interrupt are as follows:
1. Processor relinquishes control of the bus, priorities permitting.
2. When a master gains contro( it sends the processor an interrupt command and a unique memory address which contains the address of the device's service routine in Kernel virtual address space, called the interrupt vector address. Immediately following this pointer ad-dress is a word (located at vector adad-dress +2) which is to be used as a new Processor Status Word.
3. The processor stores the current Processor Status Word (PS) and the current Program Counter (PC) into CPU temporary registers.
4. The new PC and PS (the interrupt vector) are taken from the speci-fied address. The old PS and PC are then pushed onto the current stack as indicated by bits 15,14 of the new PS and the previous mode in effect is stored in bits 13,12 of the new PS. The service routine is then initiated.
These oper-ations are performed in 2.5 .usec from the time the control processor receives the interrupt command until the time it starts execut·
ing the first instruction of the service routine. This time interval assumes no NPR transfer occurred during this time interval.
5. The device service routine can cause the processor to resume the
in the temporary registers and then pushed onto the new current stack, and the new device routine is initiated.
2.6.7 Interrupt Servicing
Every· hardware device capable of interrupting the processor has a unique set of locations (2 words) reserved for its interrupt vector. The first word contains the location of the device's service routine, a·nd the second, the Processor Status Word that is to be used by the service routine.
Through proper use of the PS, the programmer can switch the opera-tional mode of the processor, alter the General Register Set in use (con-text switchil}g), and modify the Processor's Priority level to mask O'ut lower level interrupts.
There is one interrupt vector for the Program Interrupt Request_ It will generally be necessary in a multi-processing environment to determine which program generated the PIR and" where it is located in memory.
Appendix D provides an example of how this is done.