SYNCHRONOUS MODE Control Register 1

Selects Transmit and Receive clock as

o

^~ Transmit and Receive clock inPut

1~Ra\el (32X) 2-;- Rate 2 (32X) 3 - Rate.3(32X}

4 - Rate 4 (32X)

5.--: Rate 4

+-

2'(32X) (64X) 6'- Rate 4.+ 4 (32X) (128X) 7 '-'-Rate 4 -+-8 (32X) (256X)

Control Register 1 (Sync Mode continued)

Bit Name Function

3 PARITY ENABLE When set to a 1 bit, itenables check of parity on received characters only.

4 DLE STRIP/MISCELLANEOUS When set to a 1. bit andthereceiver is enabled, received charaoters which match the contents of the DLE Register are stripped out. Also parity checking is .disabled. When the receiver is not enabled this bit controls the MISCELLANEOUS output onPin 5. to be used for New Sync on a 201 Data Set. When operating with a 32X clock for 1 bit with the receiver not enabled causes the receiver bit timing to synchronize onmark"space transitions.

5 TX PARITY ENABLE/FORCE DLE When set to a 1 bit with Bit6 of Control Register 1 a 0 bit Transmit Parity is enabled, otherwise no parity is generated. When set toa 1 bit with Bit 6 a 1 bit, it causes the contents of the OLE Register to be

Control Register 2

Bit Name

2-0

3

5

7-6

transmitted prior to the next character loaded in the Transmitter Holding Register. (See description of Transparency below.) When a 1 bit of the transmitter is conditioned fortransparenl trans,-mission which implies thatidl.e filiWil1 be DLE-SYN and a DLE can be forced ahead of any character in Ihe THR by use of Bit 5 .. (See description o/Transparency.)

When.lhis bit is selloa Obit.the device is configured to provide~n inlernal dalaandcontrol loop (see Loop feature) and the Ring interrupt is disabled, When this bit is seUo a1 bit the device is in normal.fulldlJplex conflgurationand the Ring interrupt is enabled.

Function

Selects Transmit and Receive clock as follows:

0---:

Transmit and Receive clock input (1X) 1.,..-. Rate 1 (32X)

2--Rate2 (32X) 3,..- Rate 3 (32X) 4 -Rate 4 (32X)

5 ---: Rate 4 -7-2 (32Xi (64X) 6 '-.Rate4 -7-4 (32X) (128X) 7-Rate4 -7-8 (32X) (256X)

When set toa,l bit and the receiver Isenabled. received characters which match the contents ofJhe SYN Register are stripped out.

Also the SYN status bit is set with the next character. No SYN stripping occurs with aO bit.

A 1 bitselects Odd Parity and aO bit selects Even Parity. when parity is enabled.

A 0 bit selects Asynchronous Character Mode.

A 1 bUse.lects Synchronous Character Mode.

TRANSPARENCY

The Transmit Transparency mode causes Idle Fill to be the pair of characters OLE-SYN rather than a sin-gle SYN, and provides for preceding a character loaded into the THR with a OLE without the possibil-ity of an intervening OLE-SYN fill. Transparency is enabled by Bit 6 of Control Register 1, which allows force OLE to be controlled by Control Register 1, Bit 5, but the OLE-SYN fill is not activated until after the first forced OLE. All aspects ofTransparency are

dis-abled when Bit 6 is set to a 0 bit. When forcing trans-mission of a OLE, Bit 5 should be set to a 1 bit prior to loading the Transmitter Holding Register, otherwise the character in the Transmitter Holding Register may be transferred to the Transmitter Register prior to the setting of the Con'trol Bit.

STATUS

The Status Register contains the following status information:

Name TRANSMITTER HOLDING REGISTER EMPTY (THRE)

Function

This bit is a 1. bit when the Transmitter Holding Register does not contain a character and the transmitter is enabled. It isset to a 1 bit when the contents of the Transmitter Holding Register is transferred to the Transmitter Register. It is cleared to a 0 bit when the Trans-mitter Holding Register is loaded from the OAL, or when the trans-mitter is disabled.

This bit isseI toa 1 bit when the Receiver Holding Registeris loaded from IheReceiver if the Receiver is enabled. It is cleared to a 0 bit when li:le Re<;eiver Holding Register is read onto the DAL, or when the receiver is disabled.

This bilis set to.a.l bit when the previous character in the.Receiver Holding Reg ister has

not

been read, causing DR to not be reset, at the timeanew c~iOIracter is re?dy to be transferred to the Receiver Holdin!;) Register: otherwisethepit is cleared when a character is tram;ferredtotheReceiverHolding Register. It is cleared when the reGeiver is disabled.

This bit is set

loa 1

bit when the receiver and Receive parity are enabh3qll.pd the last received character has a parity error, and is set

tq

a 9b.it,if 1i:lE\! chara.cter has correct parity. When the DLEstrip.

is enal:)led t~~Re~eive, parity check is disabled and this bilis set toal, bitifthe previous character matched the contents Of the OLE Register anq,wa? stripped, otherwise it is set to a 0 bit. This bit is cleilre<j ,:",i:len the receiver is disabled. When a SYN or OLE character is stripped this bit cannot be reset.

Il'lthellsyn:ch'ronous mode this bit is set to a 1 bit if the bit after the last data bit ofa.synchronous character is a zero and the receiver is enabled. Thi3Status bit is set to a 0 bit if the bit is a one. In the synchronousrnode this bit is set to al bit when the contents of the ReCeiveLReg.!ster matGhes the contents of the SYN Register and SYNslrip is;\l91 enabled. In both modes the bit is cleared when the receiverisd~sal)led.lf SYNstrip is enabled this status bit is updated ,:",iththechar~cter received after the SYN character. When a SYN or. Dt,.Eci:laracteris stripped this bit cannot be reset.

Tl'lishit is Itlecomplement of the Carrier Detector input on Pin:,1(}.

Thisbitisthecornplementof the Data Set Ready input on Pin 33.

With.202-lype data sets. it can be used for Secondary Receive.

This ,bit i~$~H()a 1 bit when there is a ohange in rhe state of the

DataS!3t

fle!!~Y()r Qarrierqetector inputs with OTR on.,. oC!he Ring indicalor.i~ .tu;ned>()~,:"ithOTR off, Tbis bit is cleared when the Status RegistElr .isreaqontothe OAL .

7

SYNC/ASYNC O-lOOP MODE 1- NORMAL MODE

•

ASYNC

Controt Registers 1, 2 and STATUS Bit Assignments for TRUE DATA BUS, Invert for FALSE DATA BUS.

BIT

• •

^{3 2}

ASYNC ASYNC ASYNC SYNC!

O-NON BREAK MODE lTRANS, ENABLED I 0- NON ECHO MODE 0- NO PARITY ENABLED ASYNC 1-8REAK MODE 0-1V, OR 2 STOP BIT I-AUTO ECHO ,-- PARITY CHECK 0- RECEIVER

1

•

SYNC I SYNC I

ASYNC ASYNC

0-, SETS

m

O-SETS

rn

SELECTION ^MODE ENABLED ON RECEIVER, DISABLED OUT ~ 1 OUT· ,

SYNC 1- SINGLE STOP BIT PARITY GENERATION I-RECEIVER I-SETS

m

1- SETS 0i1i

O-NON TRANSMlnER SELECTION SYNC ICRl2 '" 11 ENABLED ON ENABLED OUT a OUT - 0

TRANSPARENT MODE O-OlE STRIPPING TRANSMITTER

1- TRANSMIT ASVNC NOT ENABLED

TRANSPARENT MODE ITRANS. OISABlEDI !-OLE STRIPPING SYNC O-~OUT" 1 ^ENABLED O-RECEIVER PARITY

l-mttOUT" 0 CHECK IS DISABLED

SYNC (CR12 • 01 1- RECEIVER PARITY SYNC ICRlIl • 01 O-~OUT '" 1 CHECK IS ENABLED O-NO PARITY GENERATED 1-MiSt OUT" 0

I _ TRANSMIT PARITY ENABLED SYNC ICRlI • 11 a-NO FORCE OLE , -FORCE OLE

CONTROL REGISTER 1

BIT

7

• • •

^{3 2 1}

•

SYNC/ASYNC MODE SELECT SYNC/ASYNC ASYNC SVNC/ASYNC

CHARACTER LENGTH SELECT a-ASYNCHRONOUS MODE 1-000 PARITY SELECT , - RECEIVER CLOCK DETERMINED CLOCK SELECT 00 " 8 BITS ' - SYNCHRONOUS MODE O-EVEN PARITY SELECT BY BITS 2-0

000-lX CLOCK

01 = 7 BITS O-RECEIVER CLK = RATE I

001-RATE 1 CLOCK 10 = 6 BITS

SYNC OlO-RATE 2 CLOCK

11 = 5 BITS 0" -RATE 3 CLOCK

0- NO SYN STRIP 100- RATE" CLOCK

l-SYN STRIP 101-RATE 4 CLOCK - 2

"O-RATE" CLOCK - "

111-RATE 4 CLOCK - 8

CONTROL REGISTER 2

BIT

7

• , •

^{3 2 1 0}

DATA SET CHANGE OATil, SET READY CARRIER DETECTOR FRAMING ERROR OLE OETECT OVERRUN ERROR DATA RECEIVER TRANSMITTER HOLDING

SYN DETECT PARITY ERROR REGISTER EMPTY

STATUS REGISTER

Reg A1 AO RBad WrltB

0 0 0 Control Register 1 Control RBglster 1 1 0 1 Control Register 2 Control Register 2 2 1 0 Status Register SYN & OLE Register 3 1 1 RBceiver Holding Transmitter Holding

Register Register

INTERRUPTS

The following interrupts can be generated.

Carrier On

The Carrier On interrupt occurs when the Carrier Detector input goes low and DTR is on.

Carrier

all

The Carrier Off interrupt occurs when the Carrier Detector input goes high and DTR is on.

DSR On

The DSR On interrupt occurs when the Data Set Ready input goes low and DTR is on.

DSR

all

The DSR Off interrupt occurs when the Data Set Ready input goes high and DTR is on.

VOL

Ring On

The Ring On interrupt occurs when the Ring input goes low and DTR is off.

When an interrupt condition exists the INTR output is made high. Reading the Status Register or MR will al-low INTR to go high again.

DATA BUS CONTROLS

The following Data Bus controls can be generated.

Data Request Out

This control signal occurs when the THR is empty while the transmitter is enabled.

Data Request In

This control signal occurs when the RHR is full while the receiver is enabled.

-

^TOACC

£-t ^-

^TOOH

VIH

\ II

AO.Ai.Cs

VIL

1\ J

VIH TCS

RE

\ V

VIL

1\ /

I--

TSET TRE

THLO-READ TIMING

VIL

T O S - TOH

AD.Al.es

^VIH

VIL )

Tes VIH

\

vlL

1\ J

I---

TSET

.

^TWE

THLO-WRITE TIMING

MAXIMUM RATINGS

VDD with Respect to VSS (Ground) + 15 to - 0.3V Max. Voltage to any Input with Respect to VSS + 20 to - 0.3V

Operating Temperature ooe to 70⁰e

Power Dissipation 600 mW

OPERATING CHARACTERISTICS

Storage Temp Ceramic -65°C to +150'C Plastic -55'C to ,125'C

TA

=

ooe to 70^oe, VDD

=

+ 12.0V ± .6V, Vee = + 5.0V ± .25V, VSS

=

OV

SYMBOL CHARACTERISTIC MIN TYP MAX UNITS CONDITIONS

III Input Leakage 10 uA VIN

=

VDD

ILO Output Leakage 10 uA VOUT = Vee

leeAVE VecSupply eurrent 80 mA

IODAVE VOD Supply Current 10 mA

VIH Input High Voltage 2.4 V

VIL Input Low Voltage (All Inputs) .8 V

VOH Output High Voltage 2.S V 10

=

-100 uA

VOL Output Low Voltage .45 V 10= 1.6 mA

AC CHARACTERISTICS

TA

=

ooe to 70°C, VDD

=

+ 12.0V ±0.6V, VSS

=

OV, VCC +5.0 ± .25V

SYMBOL CHARACTERISTIC MIN TYP MAX UNITS CONDITIONS

THLD AO, Al & CS Hold Time 5 ns

Tes AO, A1 & CS Width 495 ns

TSET AO, Al & es Set·Up Time 240 ns

TeYCLE Cycle Time 1000 ns

TLOW AO, Al & CS Low Time 250 ns

TMR MR Pulse Width 450 ns

READ

TRE RE Width 250 ns

TOACC Data Access from

RE

300 ns CL

=

25 pI

TOOH Data Hold from

RE

50 150 ns eL

=

25 pf

WRITE

TWE WE Width 250 ns

TOS Data Set·Up Time 250 ns

TDH Data Hold Time 100 ns

BUY/SELL TRANSACTION-ENTRY TERMINAL (CRT)

DATA COMMUNICATIONS SYSTEMS FOR STOCK BROKERAGE FIRM

,- I I

I

I

SOLC

PROTOCOL SYNCHRONOUS

I

LINK

_-"L-__ -'

BISYNC ~A:::;"'~--' PROTOCOL

I

I

I

I I I I I I

I I I I L

TO REMOTE TERMINAL

LINK

TO REMOTE TERMINAL

TO REMOTE TERMINAL

-1

DETAIL OF DATA COMMUNICATION CONTROLLER DIGITAL COMMUNICATIONS SYSTEM

The diagrams above illustrate a typical digital sys-tem employing several processing levels and digital protocols. It is flexible enough to satisfy several applications. For example, the host processor and remote terminals could be located respectively in airline reservation offices and ticket counters, travel centers and travel agencies, central bank offices and branch banks, or department stores and individual

cash registers. The exploded diagram of the Oata-Communications Controller exemplifies the use of one common circuit board design with one 40-pin socket. When the Port requires a character-oriented protocol (synchronous, asynchronous, or synchronous-bisync), the W01931 is plugged into the socket. For SOLC, HOLC or AOCCP, theW01933 is used. I n addition to storing the design cycle, sys-tem flexibility and cost savings are achieved.

WD1931A CERAMIC PACKAGE WD1931B PLASTIC PACKAGE

Information furnished by Western Digital Corporation IS believed to be accurate and reliable. However, no responsibility is assumed by Western Digital Corporation for its use; nor any mfringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation Western DI91tai Corpora-tion reserves the right to change said circuitry at any time without notice.

WESTERN DIGITAL

3128 REDHILL AVENUE. BOX 2180

C O R P O R A T I O N NEWPORT BEACH. CA 92663 (714) 557-3550.TWX 910-595-1139

FEATURES

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c o

R p

o

R A T /

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