present on the address bus, data bus, and the read/write (R/Wlline during each cycle of each instruction.
The information is useful in comparing actual with ex-pected results during debug of both software and hardware as the program is executed. The information is categorized in groups according to addressing mode and number of cycles per instruction. In general, instructions with the same ad-dressing mode and number of cycles execute in the same manner. Exceptions are indicated in the table.
Note that during MPU reads of internal locations, the resultant value will not appear on the external data bus ex-cept in mode O. "High order" byte refers to the most signifi-cant byte of a 16-bit value.
•
MC6801 U4, MC6803U4
TABLE 9 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes
Immed Direct Index Extnd Inherent Boolean! 5 4 3 2 1 0
Pointer Operations MNEM Op - # Op - # Op - # Op
-
# Op-
# Arithmetic Operation H I N Z V C Compare Index Register CPX 8C 4 3 9C 5 2 AC 6 2 BC 6 3 x-M:M+ 1· · I I I I
Decrement Index Register DEX 09 3 1 X-1-X
· · • I · ·
Decrement Stack Pointer DES 34 3 1 SP-l-SP
· · · · · ·
Increment Index Register INX 08 3 1 X+l-X
· · I ·
Increment Stack Pointer INS 31 3 1 1 SP+l-SP
· · · · ·
Load Index Register LDX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M-XH.(M+l)-X
· · I t
R·
Load Stack Pointer LDS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M-SPH·(M+ll-SPL
· · I I
R·
Store Index Register STX DF 4 2 EF 5 2 FF 5 3 XH-M,XL -(M+l)
· · I I
R·
Store Stack Pointer STS 9F 4 2 AF 5 2 BF 5 3 SPH-M,SPL -(M+1)
· · I I
R·
Index Reg -Stack Pnlr-Index Register Stack Pointer TXS TSX 35 3 30 3 1 X 1 SP+l-X l-SP
· · · · · · · · · · · ·
II
Add Push Data PSHX ABX 3A 3 3C 4 1 1 XL -B+X-X XH - MSp,SP l-SP MSp,SP-1 -SP· · · · · · · ·
Pull Data PULX 38 5 1 SP+l-SP,MSp-XH SP+l-SP,MSp-XL
· · ·
TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 21
Condition Codes
Accumulator and Immed Direct Index Extend Inher Boolean 5 4 3 2 1 0
Memory Operations MNEM Op
-
# Op - # Op - # Op - # Op - # Expression H I N Z V CAdd Accumulators ABA 1B 2 1 A+B-A
I · I I I I
AddBtoX ABX 3A 3 1 OO:B+X-X
· · ·
Add with Carry ADCA 89 2 2 99 3 2 A9 4 2 B9 4 3 A+M+C-A
I · I I I I
ADCB C9 2 2 D9 3 2 E9 4 2 F9 4 3 B+M+C-B
I I I ! I
Add ADOA 8B 2 2 9B 3 2 AS 4 2 BB 4 3 A+M-A
I
II I I
ADOB CB 2 2 OB 3 2 EB 4 2 FB 4 3 B+M-A
I I I I I
Add Double AOOD C3 4 3 03 5 2 E3 6 2 F3 6 3 D+M:M+l-D
· · I I I I
And ANDA ANOB C4 84 2 2 2 94 2 D4 3 3 2 2 A4 4 E4 4 2 2 B4 4 F4 4 3 3 A·M-A B·M-B
· · • II I II I
R R· ·
Shift Left, Arithmetic ASLA ASLB ASL 68 6 2 78 6 3 48 68 2 2 1 1
@]-i
b7IIIIIII1 -
bO - 0· · · · · II
IIII
Shift Left Double ASLD 05 3 1
· IL
Shift Right, Arithmetic ASR 67 6 2 77 6 3
qililllll-@J · It I I
ASRA 41 2 1
· I I I I
ASRB 57 2 1 b7 bO
· I I I I
Bit Test BITA 85 BITB C5 2 2 2 2 95 05 3 3 2 2 A5 4 E5 4 2 85 4 2 F5 4 3 3 A·M B·M
· · I! I I I
R R· ·
Compare Accumulators CBA 11 2 1 A-B
· · II I I I
Clear CLRA CLRB CLR 6F 6 2 7F 6 3 4F 5F 2 2 1 oo-A 1 oo-B oo-M
· · · · ·
R R S R R S S R R R R RCompare CMPA 81 CMPB C1 2 2 2 2 01 3 91 3 2 2 A1 E1 4 4 2 2 B1 F1 4 4 3 3 A-M B- M
· · · I I I !
1's Complement COMA COMB COM 63 6 2 73 6 3 43 53 2 2 1 A - A 1 B-B M-M
· · · · · I I I I
R R S R S S3-122
MC6801 U4, MC6803U4
TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 21
Condition Codes
Accumulator and Immed Direct Index Extend Inher Boolean 5 4 3 2 1 0
Memory Operations MNEM Op # Op - # Op - # Op - # Op - # Expression H I N Z V C
Decimal Adjust, A OAA 19 2 1 Adj binary sum to BCD
· · t t t t
Decrement OECA OECB DEC 6A 6 2 7A 6 3 4A 2 5A 2 1 1 M - l - M A - l - A 8 - 1 - 8
· · · · · • I t t t t t t t t · · ·
Exclusive OR EORA EORB C8 2 88 2 2 2 08 3 2 EB 4 2 F8 4 3 98 3 2 AB 4 2 BB 4 3 A$M-A B$M-B
· · · • t t t t
R R· ·
Increment INCA INCB INC 6C 6 2 7C 6 3 4C 2 5C 2 1 1 M+l-M A+l-A 8+1-8
· · · · · · t t t t t t t t t · · ·
Load Accumulators LOAA LOAB C6 2 2 06 3 2 E6 4 2 F6 4 3 88 2 2 96 3 2 A6 4 2 B6 4 3 M-A M-B
· · · · I t t t
R R· ·
load Double LOO CC 3 3 DC 4 2 EC 5 2 FC 5 3 M:M+l-D
· · t t
R·
Logical Shift, Left LSL 68 6 2 7B 6 3
· · t t t t
LSLA 48 2 1
@]-llllllill
- 0· · t t t t
LSLB 68 2 1 b7 bO
· · t t t t
LSLO 05 3 2
· · t t t t •
Shift Right, Logical LSRA LSRB LSRO LSR 64 6 2 74 6 3 44 54 04 2 3 2 1 1 1 o
-IIIIIIIII-@]
b7 bO· · · · · · · ·
R R R RJ t t t t t t t t t t t
Multiply MUL 3D 10 1 AxB-D
· · · t
2'5 Complement (Negate) NEG 60 6 2 70 6 3 OO-M-M
· · t t t t
NEGA 40 2 1 OO-A-A
· • t t t t
NEGB 50 2 1 00-B-B
· · t t t t
No Operation NOP 01 2 1 PC+ l-PC
· · · ·
Inclusive OR DRAA 8A 2 DRAB CA 2 2 DA 3 2 EA 4 2 FA 4 3 2 9A 3 2 AA 4 2 BA 4 3 A+M-A B+M-B
· · · • I I t t
R R· ·
Push Data PSHA PSHB 36 3 37 3 1 1 A-Stack B-Stack
· · · · · · ·
Pull Data PULB PULA 32 4 33 4 1 1 Stack-A Stack-B
· · · · · · · · · ·
Rotate Left ROLA ROL 69 6 2 79 6 3 49 2 1
@]-lllllllll-jg · · · · ! t t t t t t t
ROLB 59 2 1 b7 bO
· · t t t t
Rotate Right RORA ROR 66 6 2 76 6 3 46 2 1
@J-11111111f-13 · · · · t t t t t t I t
RORB 56 2 1 b7 bO
· · t t t t
Subtract Accumulator SBA 10 2 1 A-B-A
· · t t t t
Subtract with Carry SBCA 82 2 2 92 3 2 A2 4 2 82 4 3 A-M-C-A
· · t t t t
SBCB C2 2 2 D2 3 2 E2 4 2 F2 4 3 B-M-C-B
· · t t t t
Store Accumulators STAA STAB STO DO 4 D7 3 2 E7 4 97 3 2 A7 4 2 B7 4 3 2 ED 5 2 2 F7 4 FD 5 3 3 A-M B-M D-M"M+l
· · · · · · t t t t t t
R R R· · ·
Subtract SUBA 80 2 2 90 3 2 AO 4 2 BO 4 3 A-M-A
· · t t t t
SUBB CO 2 2 DO 3 2 EO 4 2 FO 4 3 B-M-B
· · t t t t
Subtract Double SUBD 83 4 3 93 5 2 A3 6 2 B3 6 3 D-M:M+l-D
· · t t t t
Transfer Accumulator TAB TBA 16 2 1 A-B 17 2 1 B-A
· · · · t t t t
R R· ·
Test, Zero or Minus TSTA TSTB TST 60 6 2 7D 6 3 40 5D 2 2 1 A-OO 1 B-OO M-OO
· · · · · t t t t t t
R R R R R RThe conditIon code regIster notes are l,sted after Table 12.
II
TABLE 12 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS
Operations MNEM
Clear Carry Clear Interrupt Mask Clear Overflow Set Carry Set Interrupt Mask Set Overflow Accumulator A - eCA CCA - Accumulator A
LEGEND
Op Operation Code (Hexadecimall - Number of MPU Cycles X Ari1hme1ic Mul1iply
+ Boolean Inclusive OR
CONDITION CODE SYMBOLS H Half-carry from bi1 3
Condition Code Register 5 4 3 2 1 0
MC6801 U4, MC6803U4
TABLE 13 - INSTRUCTION EXECUTION TIMES IN E CYCLES
ADDRESSING MODE ADDRESSING MODE
!
..
." C"
i j
" u
.""
c: ."" • E ..,
~E ! !
"
~.5 c ·
w .".:
.c.:
a:"
;
."C
"
ij
..
."U ."
" E
.~co c:
·
E ! !
..
.5 c • ...
.cw .E
.:
ABA
• • • •
2•
INX• • • •
3ABX
• • • •
3•
JMP• •
3 3•
ADC 2 3 4 4
• •
JSR•
5 6 6•
ADD 2 3 4 4
• •
LOA 2 3 4 4•
AD DO 4 5 6 6
• •
lDD 3 4 5 5•
AND 2 3 4 4
• •
lOS 3 4 5 5•
ASl
• •
6 6 2•
LOX 3 4 5 5•
ASlD
• • • •
3•
LSL• •
6 6 2ASR
• •
6 6 2•
BCC
• • • • •
3BCS
• • • • •
3BEQ
• • • • •
3BGE
• • • • •
3LSLD
• • • •
3LSR
• •
6 6 2lSRD
• • • •
3MUl
• • • •
10•
NEG
• •
6 6 2• ..
BGT
• • • • •
3 NOP• • • •
2•
BHI
• • • • •
3 ORA 2 3 4 4• •
BHS
• • • • •
3 PSH• • • •
3•
BIT 2 3 4 4
• •
PSHX• • • •
4•
BlE
• • • • •
3 PUl• • • •
4•
BLO
• • •
3 PULX• • • •
5•
BLS
• • •
3 ROL• •
6 6 2..
BlT
• •
3 ROR• •
6 6 2•
BMI BNE
•
3 RTI• • • •
10•
•
3 RTS• • • •
5•
BPL
•
3 SBA• • • •
2•
BRA
•
3 SBC 2 3 4 4• •
BRN
•
3 SEC• • • •
2•
BSR
•
6 SEI• • • •
2•
BVC
•
3 SEV• • • •
2•
BVS
•
3 STA•
3 4 4• •
CBA 2
•
STD•
4 5 5•
CLC 2 STS
•
4 5 5•
CLI 2 STX
•
4 5 5•
CLR 6 6 2 SUB 2 3 4 4
•
CLV
• •
2 SUBD 4 5 6 6•
CMP 2 3 4 4
•
SWI• • • •
12COM
• •
6 6 2 TAB• • • •
2CPX 4 5 6 6
•
TAP• • • •
2DAA
• • • •
2 TBA• • • •
2DEC
• •
6 6 2 lPA• • • •
2DES
• • • •
3 TST• •
6 6 2DEX EOR
•
2• • •
3 4 4 3 TSX• • • •
3•
TXS• • • •
3INC
• •
6 6•
WAI• • • •
9INS
• • • •
3•
Data from Accumulator Dpcade First Subroutine Opcode Return Address I Low Order Byte) Return Address I High Order Byte)MC6801 U4, MC6803U4
Operand Destination Address Opcode Address Subroutine Starting Address Stack PointerDestination Address (High Order Byte) Destination Address (Low Order Byte) Data from Accumulator
Opcode Current Operand Data
Low Byte of Restart Vector
I
Index Register+ Offset Index Register+ Offset + 1Address Bus FFFF Opcode Address Opcode Address + 1 Address Bus FFFF Index Register+ Offset Stack Pointer Current Operand Data Low Byte of Restart Vector First Subroutine Opcode Return Address (Low Order Byte) Return Address (High Order Byte)
*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF
3-128
MC6801 U4, MC6803U4
Contents of Condition Code RegisterII
I
Vector Address FFFA IHex) Vector Address FFFB (Hex) Subroutine Starting Address Stack PointerContents of Condition Code Register from Stack Contents of Accumulator B from Stack Contents of Accumulator A from Stack Index Register from Stack (High Order Byte) Index Register from Stack ILow Order Byte) Next Instruction Address from Stack (High Order Byte) Next Instruction Address from Stack (Low Order Byte) Opcode Contents of Condition Code Register Irrelevant Data
Address of Subroutine (High Order Byte) Address of Subroutine (Low Order Byte)
Opcode
<f' ...
Co)
...
FIGURE 24 - SPECIAL OPERATIONS
JSR, Jump to Subroutine
1
aSR, Branch To Subroutine
Main Program
RTS. Return from Subroutine Subroutine Sf' Stack
~E??RTs] e)
- =-Stack Pointer After Execution K "" a-bit Unsigned ValueSWI, Software Interrupt Main Program
R~ I
$3F=SWIIe)-WAI, Wait for Interrupt
Main Program ~
~ I
S3E=WAI1Lv'
RTN
RTI, Return from Interrupt Interrupt Program
~
$3B=RTII¢
X+K Next Instruction
K
•
MC6801 U4, MC6803U4
APPENDIX
CUSTOM MC6801U4 ORDERING INFORMATION
A.l CUSTOM MC6801U4 ORDERING INFORMATION The custom MC6801U4 specifications may be transmitted to Motorola in any of the following media:
1) EPROMs 2) MOOS diskette
The specification should be formatted and packed. as i~
dicated in the appropriate paragraph below. and mailed prepaid and insured with a cover letter (see Figure A-21 to:
Motorola Inc.
3501 Ed Bluestein Blvd.
Austin, Texas 78721 Mail Drop L-13
A copy of the cover letter should also be mailed separate-ly.
A.2 EPROMs
MCM2708 and MCM2716 type EPROMs, programmed with the custom program (positive logic sense for address and data). may be submitted for pattern generation Both the MCM2708s and MCM2716s must be clearly marked to in-dicate which PROM corresponds to which address space EXORciser is a registered trademark of Motorola Inc.
UNICORN is a trademark of Motorola Inc.
($FOOO-$FFFFI. See Figure A-1 for recommended marking procedure.
M ~
FIGURE A-1
M ~
xxx
~ Customer IDAfter the EPROMs are marked, they sould be placed in a conductive IC carrier and securely packed. Do not use styrofoam.
A.3 DISKETIE (MOOS)
The start/end location should be written on the label using EXORciser format.
...----MC6801U4L1 UNICORN Monitor----, An MC6801 U4 may be purchased without specify-ing the ROM pattern. This standard part is labeled as MC6801U4L 1 and contains a 2K monitor (UNICORN) in the ROM. This monitor may be used to evaluate and debug a program under development Details and a source listing are specified in the UNICORN Monitor Reference Manual M68UNICORNID11.
FIGURE A-2
Customer Name ______________________________________________________________________________________ _ Address __________________________________________________________________________________________ __
State _____________________________________________________ Cny _____________________ Z,p __________ __
Phone { ___ I' _______________________________________________________ Extension _______________________ _ Contact Ms/Mr ______________________________________________________________________________________ _ CustomerPart# ____________________________________________________________________________________ ___
Package Type
o
Ceramico
PlasticMarking
o
Standardo
SpeCial Pattern Mediao
2708 EPROMo
2716 EPROMo
Diskette IMDOS}o
OTHERISeeNotel ________________________________________________________________________________ _ NOTE: Other media require prior factory approvalSignature ______ -:-__________________________________________________________________________________ _ TItle ____________________________________________________________________________________________ ___