Advance Information

MICROCOMPUTER/MICROPROCESSOR (MCU/MPU) The MC6801U4 is an 8-bit single-chip microcomputer unit (MCU) which enhances the capabilities of the MC6801 and significantly enhances the capabilities of theM6800 Family of parts. It includes an MC6801 microprocessor unit (MPU) with direct object-code com-patibility and upward object-code comcom-patibility with the MC6800. Ex-ecution times of key instructions have been improved over the MC6800 and the new instructions found on the MC6801 are included. The MCU can function as a monolithic microcomputer or can be expanded to a 64K byte address space. It is TTL compatible and requires one

+

5-volt power supply. On-chip resources include 4096 bytes of ROM, 192 bytes of RAM, a serial communications interface (SCIl, parallel'I/O, and a 16-bit six-function programmable timer. The MC6803U4 can be con-sidered an MC6801 U4. operating in modes 2 or 3; i.e., those that do nbt

• Internal Clock Generator with Divide-by-Four Output

• Serial Communications Interface (SCIl

• 16-Bit Six-Function Programmable Timer

• Three Output Compare Functions

• Two Input Capture Functions

• Counter Alternate Address

• 4096 Bytes of ROM (MC6801U4)

Package Type Frequency (MHzl Temperature Generic Number Ceramic 1.0 O°C to 70°C MC6801U4L1

(HIGH-DENSITY N-CHANNEL, SILICON-GATEI

MICROCOMPUTER/

•

MC6801 U4, MC6803U4

MC6801U4 MICROCOMPUTER FAMILY BLOCK DIAGRAM

P37 P36 P35 P34 P33 P32 P31 P30 SC2 SCl

P47 P46 P45 P44 P43 P42 P41 P40

, - - - Expanded Multiplexed

r---=

^E~panded Non-Multiplexed J

I

Single Chip

A7/07 07 1/0 A6/06 06 1/0 A5/05 05 1/0 A4/04 04 1/0 A3/03 03 1/0

A2/02 02 1/0 iRQi

Al/01 01 1/0 AO/OO DO 1/0 R/W R/W OS3 AS lOS iS3

A15 A7 1/0 A14 A6 1/0 A13 A5 1/0 A12 A4 1/0 All A3 1/0 Al0 A2 1/0

A9 Al 1/0

A8 AO 1/0

NOTE: No functioning ROM in MC6803U4

3-92

.... - - - t - - t .... - .. I P20

~---1~~+-

. .

IP21

.... - - + ....

't--If-~ P22

J-oIE-...

+--t--+-l~ P23

~""'++-+--If-~ P24

Pl0 Pl1 P12 P13 P14 P15 P16 P17

TINl TOUTl SCLK

1/0 1/0 1/0 ROATA 1/0 TDATA 1/0

TIN2 1/0 TOUT2 1/0 TOUT3 1/0 1/0 1/0 1/0 1/0 1/0

MC6801 U4, MC6803U4

MAXIMUM RATINGS

Rating Symbol Value Unit

Supply Voltage VCC -0.3 to + 7.0 V

Input Voltage Vin -0.3 to +7.0 V

Operating Temperature Range TA TH to TL "C

MC6801U4, MC6803U4 - 0 to 70

MC6801U4C, MC6803U4C -40 to 85

Storage Temperature Range Tstg -55 to + 150

'c

THERMAL CHARACTERISTICS

Characteristic Symbol Value Rating

Thermal Resistance

Plastic °JA 50 'C/W

Ceramic 50

POWER CONSIDERATIONS The average chip-JunctIOn temperature, T J, in "C can be obtained from:

Tj=TA+IPO·eJAI Where:

fA'" Ambient Temperature,

'c

This device contains circuitry to protect the in-puts against damage due to high static voltages or electric fields; however, it is advised that nor-mal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper opera-tion it IS recommended that V_ln and Vout be con-strained to the range VSS =::; (Vln or Vout):S; Vee

Input protection IS enhanced by connecting unused inputs to either VOD or VSS

III

eJA'" Package Thermal Resistance, Junctlon-to-Ambient, °C/W PO"'PINT+PPORT

PINT'" ICC x VCe. Watts - Chip Internal Power PPORT'" Port Power Oissipatlon, Watts - User Oetermined

For most applications PPORT<!{ PINT and can be neglected. PPORT may become significant if the device is configured to drive Darlington bases or sink LED loads.

An approximate relationship between Po and T J Ilf PPORT IS neglected I is:

Po = K ⁺ IT j + 273"CI 121

Solving equations 1 and 2 for K gives:

K = PO.IT A + 273'CI + ejA·P 0 2 131

Where K IS a constant pertaining to the particular part. K can be determined from equation 3 by measuring Po lat equilibriuml for a known T A Using this value of K the values of Po and T J can be obtained by solving equations 111 and 121 iteratively for any value of T A.

CONTROLTIMINGIVCC-50V +5% VSS-O TA-Ot070'CI - -

-MC6801U4 -MC6801U4-1

Characteristic Symbol MC6803U4 MC6803U4-1 Unit

Min Max Min Max

Frequency of Operation fo 0.5 1.0 0.5 1.25 MHz

Crystal Frequency fXTAL 2.0 4.0 2.0 5.0 MHz

External Oscillator Frequency 4 fa 2.0 4.0 2.0 5.0 MHz

Crystal Oscillator Startup Time tre - 100 - 100 ms

Processor Control Setup Time tpcs ²⁰⁰ - 170 - ns

II

MC6801 U4, MC6803U4

DC ELECTRICAL CHARACTERISTICS IVCC-5

- a

Vdc ±5% VSs-O TA -^-

- h

to TH unless otherwise notedl

MC6801U4, MC6801U4C,

MC6803U4 MC6803U4C

Characteristic Symbol Min Max Min Max Unit

Input High Voltage RESET VIH VSS+4.0 VCC VSS+4.0 VCC V

Other Inputs' VSS+2.0 VCC VSS+2.2 VCC

Input Low Voltage All Inputs' VIL VSS-0.3 VSS+0.8 VSS-0.3 VSS+0.8 V

Input Load CUffent Port 4 lin 0.5 0.8 mA

SCI

-

0.8 - _1.0

Input Leakage CUffent

IVin =

a

to 5.5 VI NMI.IRQ1, RESET lin - 2.5 - 5.0 ~A

Hi-Z IOff-Statel Input CUffent

IVin = 0.5 to 2.4 VI Port I, Port 2, Port 3 ITS I - 10 - 20 ~A

Output High Voltage

IILoad= -65~A, VCC= Mini Port4, SCI, SC2 VOH VSS+2.4 - _{VSS + 2.4}

-

V

IILoad= -100I'A, VCC= Mini Other Outputs VSS+2.4 - _{VSS + 2.4}

-I

Output Low Voltage

IILoad=2.0 mA, VCC= Mini All Outputs VOL

-

VSS+0.5 - VSS+0.6 V

Darlington Drive Current

IVO=I.5VI Port 1 IOH 1.0 4.0 1.0 5.0 mA

Internal Power Dissipation

IMeasured at T A = TL in Steady-State Operation I , " PINT - ₁₂₀₀ - 1500 mW Input Capacitance

IVin=O, TA=25'C, Port 3, Port4, SCI Cin

-

12.5 - 12.5 pF

fo= 1.0 MHzl Other Inputs

-

^{10.0 - 10.0}

VCC Standby Powerdown VSBB 4.0 5.25 4.0 5.25 V

Powerup VSB 4.75 5.25 4.75 5.25

Standby CUffent Powerdown ISBB - 3.0

-

3.5 mA

*

Except mode programming levels, see Figure 16.

"Negotiable to -100 I'A Ifor further information contact the factoryl.

' " For the MC6801U4/MC6803U4 TL =O'C and for the MC6801U4C/MC6803U4C

h

= -40' C PERIPHERAL PORT TIMING lRefer to Figures 1-41

Characteristics Symbol Min Typ Max Unit

Peripheral Data Setup Time tpDSU 200

- -

ns

Peripheral Data Hol9 Time tpDH 200 - - ns

Delay Time, Enable Positive Transition to 053 Negative Transition .tQ£Dl

_.

- ₃₅₀ ns Delay Time, Enable Positive Transition to 053 Positive Transition tOSD2 - - 350 ns Delay Time, Enable Negative Transition to Peripheral Data Valid

Port 1 tpWD - - ₃₅₀ ns

Port 2, 3, 4 - - ₃₅₀

Delay Time, Enable Negative Transition to Peripheral CMOS Data Valid tCMOS -

-

2.0 ~s

Input Strobe Pulse Width tpWIS 200 - - ns

Input Data Hold Time tlH 50 - - ns

Input Data Setup Time \is ^{20 - - ns}

3·94

MC6801 U4, MC6803U4

FIGURE 1 - DATA SETUP AND HOLD TIMES IMPU READ)

~~~:~~~ """" J..L r t +

-FIGURE 2 - DATA SETUP AND HOLD TIMES IMPU WRITE)

P40-P47 _ _ _ - J ~ _ _ _ ""';I[""

Inputs"

"t+---tCMOS-j

_ _ _ _ _ _ _ t_pw_Ox-l/

J -- --

^{0.7 Vee}

All Data

Port Outputs Data Valid

P30-P37

Inputs" _ _ _ _ _ _ _ _ - ' .. Port 3 non-latched operation (Latch enable = Q)

FIGURE 3 - PORT 3 OUTPUT STROBE TIMING IMC6801U4 SINGLE-CHIP MODE)

Address Bus

OS3

MPU Access of Port 3"

($00061

* Access matches output strobe select

(aS

S ::::: 0, a read;

as

S = 1, a write) NOTES:

10 k pullup resistor required for port 2 to reach 0 7 Vee Not applicable to P21

Port 4 cannot be pulled above Vee

IS3

FIGURE 4 - PORT 3 LATCH TIMING (MC6801U4 SINGLE-CHIP MODE)

P30 P37 ~ Data Valid

U,.---Inputs

----1'}- ---{ \

NOTE: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

FIGURE 5 - CMOS LOAD

Test POint

FIGURE 6 - TIMING TEST LOAD PORTS 1, 2, 3, AND 4

Dans le document II II (Page 138-142)