Storage access times stated in this guide are obtainable, assuming the four logical memories required are free when requested and accessed

concurrently with no interference from other components.

Processor Storage

Logical Logical Logical Logical

Memory Memory Memory Memory

1 ¹ 1 1

Jl

Storage Control Unit

"

I

^Channel Processor Storage Control

I

^Channel

~ ^:

High-Speed ^t

- ^...

^{Channel Buffer}

-

^,

^...

Buffer and

Storage Bus Controls

Controls r'-'

,.

....

Channel

Buffer Buffer

Storage Storage

I ^~

4 buffers/channel

Channel

I

^Channel

~

Instruction Execution

Unit Unit

Central Processing Unit (CPU)

Figure 10.15.2. Model 165 storage components and controls

17

Error checking and correction (ECC) hardware provides automatic detection and correction of all single-bit processor storage errors and detection, but not correction, of all double-bit and most multiple-bit errors. The ECC feature is discussed fully in the RAS section.

The Model 165 also supports a byte boundary alignment facility for processor storage. The presence of the byte-oriented operand function allows the storage operands of unprivileged instructions (RX and RS formats) to appear on any byte boundary without causing a specification program interrupt. Without this facility, operands must be aligned on integral boundaries, that is, on storage addresses that are integral multiples of operand l~ngths. Byte orientation is standard and does not apply to alignment of instructions or channel command words (CCW's).

Use of byte alignment in a program degrades instruction execution performance. However, byte orientation can be used effectively in commercial processing to eliminate the padding bytes added within records and to blocked records to insure binary and floating-point field alignment. The smaller physical record that results from the elimination of padding bytes requires less external storage and increases effective I/O data rates. I/O-bound commercial programs, in which throughput is in almost direct proportion to the I/O data rate, can achieve performance improvement by using byte alignment for binary and floating-point data.

A program written to use byte boundary alignment will not necessarily run on a System/360 model that does not have the feature. Therefore, programs that are to run on both the Model 165 and on System/360 models without byte orientation should be written to adhere to integral

boundary rules.

Processor Storage Reconfiguration

If a processor storage box develops a malfunction, i t can be configured out of the system by use of the storage configuration plugboard in the system console. Then the operating system can be re-IPLed and the system can continue operating with reduced available storage. The configuration indicated by the plugboard is established during a power-on sequence or a system reset operation.

The user has the ability to remove one or more storage boxes from the operative system and reconfigure the addressing of the remaining boxes to achieve consecutive storage addressing. Interleaving is reduced from four-way to two-way if the configuration consists of an odd number of boxes. Therefore, four-way interleaving can be maintained in systems with four or six processor storage boxes by removing a pair of boxes instead of the malfunctioning box only. A pair must be removed in a 3072K (six-box) system as a 2560K configuration is not supported.

Serial operation is possible also and will be used primarily by customer engineers.

The configuration panel is relatively simple to use. The operator inserts plugs into the appropriate holes in the panel to describe the processor storage configuration: number of boxes (one to six) using up to three plugs, box addressing sequence (box reversals) using up to two plugs, and interleaving (four-way, two-way, or serial) using up to two plugs.

With the few reversal combinations defined, any box can be placed in the first or last box addressing position. Assume box 2 in a six-box configuration is to be configured out of the operational system.

(Refer to Figure 10.15.1, in which box numbers also indicate the

sequential positioning o~ consecutive processor storage box addressing.) Boxes 1 and 2 would be vertically reversed in position with boxes 3 and 4, respectively, and then with boxes 5 and 6, respectively. Box

2 is then in the last (or highest) addressing position and an inline ripple (discussed below) can be performed on i t . If box 1 is the malfunctioning box, a horizontal reversal of boxes 3, 5, and 1 with boxes 4, 6, and 2, respectively, puts box 1 in the highest addressing position. (The ascending addressing sequence of the boxes is then

4-3, 6-5, 2-1.) Storage Ripples

Five storage ripple functions are implemented in Model 165 hardware as maintenance aids for use by customer engineers. (A ripple is a nonprogrammed read or write of ones or zeros through every available storage address for the purpose of locating a malfunction.) A ripple is provided for ROS,

wes,

local storage, and processor storage that requires dedication of the system to the ripple function. However, an inline processor storage ripple also is implemented. I t can be executed on a malfunctioning storage box that has been configured out of the operational system while processing continues. (The processor storage box must be in the highest addressing position.) An inline ripple is not provided for the Model 65, which therefore requires total system unavailability during processor storage rippling. In addition, there is no reconfiguration capability for main storage boxes in

uniprocessor Model 65 systems.

HIGH-SPEED BUFFER STORAGE

The increase in the internal performance of the Model 165 is achieved largely by the inclusion of a high-speed buffer storage unit. The

8K buffer is a standard feature and provides high-speed data access for CPU fetches. Installation of the optional Buffer Expansion feature permits inclusion of an additional 8K of buffer storage.

The buffer has an 80-nanosecond cycle. The CPU can obtain eight bytes from the buffer in two cycles, or 160 nanoseconds, and a request can be initiated every cycle. This compares with 1.44 microseconds

(or 18 cycles) required to obtain eight bytes of data directly from processor storage. The conceptual data flow in the Model 165 is pictured in Figure 10.15.3.

Buffer storage control and use is handled entirely by hardware and is transparent to the programmer, who need not adhere to any particular program structure in order to obtain close to optimum use of the buffer.

The buffer algorithm implemented in the Model 165 is very similar to that used in the System/360 Model 195. Sample job step executions have shown that in a Model 165 the data accessed by the CPU is in the buffer 95~ of the time on the average.

19

Processor Storage

~\

^Channel

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^{8 Bytes Channel}

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^{Logical Memory Box}

CPU

Logical Memory

Instruction

-0-Unit

8 Buffer

Execution Bytes Storage

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Bytes

fr

^Logical

Memory 8 Bytes

Box

Dans le document A Guide to the IBM System/370 Model 165 (Page 24-27)