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256 Block Address Registers
256 Blocks
Addresses 0 - 2047 Addresses 2048 - 4096
Processor Storage Address Bits
Bits 8-21 20-26 21-26 27-28 29-31
Used for address compare
Used to reference 16K buffer columns Used to reference SK buffer columns
Used to reference doubleword within a block Used to reference byte within doubleword
Figure 10.15.5. Processor storage address format for buffer reference
Buffer Reference Bits
0-1 Generated as result of address compare; this two-bit encoded field represents block in buffer column containing desired data
2-8 3-8 8-10
Used to reference column for 16K buffer (processor storage address bits 20-26)
Used to reference column for SK buffer (processor storage address bits 21-26)
Used to reference doubleword within a block (processor storage address bits 27-2S)
Figure 10.15.6. Buffer address format
Buffer contents and buffer block assignment are controlled by an address array, shown in Figure 10.15.4, and a special replacement array. The address array, like the SK buffer, is divided into 64
columns consisting of four block address registers each such that there is a one-for-one correspondence between address array registers and blocks in the buffer. An address array block register contains the 14-bit processor storage block address from bits S-21 of the processor storage address of the data contained in its corresponding buffer block. When a CPU to processor storage reference is made, the four appropriate address array column registers (14-bit block addresses) are interrogated to determine whether the requested data is currently in the buffer.
The replacement array is used to maintain knowledge of the activity of the data blocks within each of the buffer columns. When an SK
buffer is present, the array consists of 64 logic-controlled activity lists, one list for each column in the buffer. A list contains four entries, one for each buffer block in its column. A block's entry is placed at the top of the list for its column when the buffer block is referenced during a CPU fetch operation. This approach insures that the block used longest ago within a given column is at the bottom of the list. When a block within a buffer column has to be assigned and loaded, because the data requested by the CPU is not in the buffer, the buffer block at the bottom of a column activity list is allocated.
Thus, the more active data is maintained in the buffer.
The SK buffer operates as follows. When the CPU requests data, bits 21-26 of the data's processor storage address are used to obtain a buffer column address. The 14 high-order bits of the processor storage address are then compared to the address in each of the four block address registers in that buffer column in the address array.
If an equal compare occurs for an address in one of the registers in the address array and the valid trigger for that block is on in the buffer, the appropriate doubleword from the buffer block is sent to the CPU as determined by bits 27 and 28 of the processor storage address. A processor storage reference is not made. The referenced buffer block is put at the top of its column activity list in the replacement array.
If the desired data block is not in the buffer column interrogated, the requested data must be fetched from processor storage, sent to the CPU, and stored in the buffer. The replacement array entry for the column involved is inspected and the buffer block at the bottom of the activity list is assigned to receive the requested data from processor storage. Four processor storage references, one cycle apart, are made to obtain the 32 consecutive bytes and place them in the
assigned buffer block. The valid trigger for the buffer block is set on and the 14 high-order processor storage address bits are placed in the appropriate column within the address array. The first doubleword fetched from processor storage is the one containing the data required by the CPU. I t is sent to the cpu as well as to the buffer so that processing can continue as soon as possible.
Assuming no channel interference, a 32-byte buffer block can be filled from processor storage in 1.44 microseconds (or 18 cycles) with four-way interleaving utilized. One buffer block can be loaded every 2 microseconds (25 cycles), assuming no interference.
10:20 CHANNELS GENERAL DESCRIPTION
The channels available on a System/370 Model 165 are functionally compatible with those of System/360 models. Combinations of 2870 Multiplexer, 2860 Selector, and 2880 Block Multiplexer channels can be attached to a Model 165. If the Extended Channels special feature is installed, up to twelve channels can be connected to a single Model 165 to provide an aggregate channel data rate in excess of nine
megabytes, twice the rate possible on a Model 65.
The 2870 and 2860 channels that attach to the Model 165 are the same as those used on a Model 65 but have minor hardware changes (as is true when these channels are attached to System/360 Models 75 and up). When a Model 165 replaces a Model 65 or 75, the 2870/Model 165 and 2860/Model 165 features can be field installed on the existing
2870 and 2860 channels, respectively, so that the latter can be attached to the Model 165.
The standard number of addressable channels permitted on a Model 165 is seven. Any combination of one or two 2870 Multiplexer, up to six 2860 Selector, and up to six 2880 Block Multiplexer channels can be attached up to the limit of seven channels. If the optional Extended Channels feature 15 installed, the maximum nQ~ber of each type of
channel that can be included in the twelve channels permitted is:
• 2870 Multiplexer - two. (The first must have address 0, the second can be assigned an address from 1 to 6.)
• 2860 Selector - six. (Addresses 1 through 6 can be assigned.)
• 2880 Block Multiplexer - eleven. (Addresses 1 through 11 can be assigned.)
Model 165 channels are not integrated with the CPU. Channels compete with each other and the CPU only for processor storage accesses and, therefore, cause a minimum of CPU interference. A 2870, 2860, or 2880 24
channel contains the hardware required to control its I/O operations (channel registers, local storage, control functions, buffers, etc.).
A channel interferes with the Model 165 CPU if the CPU accesses a
logical memory that is busy because of a channel operation. Contention between channels and the CPU for processor storage is reduced
drastically by the use of high-speed buffer storage, which eliminates CPU to processor storage fetches for approximately 95~ of the fetches required.
The standard instruction set also includes a new I/O instruction called HALT DEVICE. This instruction is specifically designed to stop an I/O operation on a particular device on a multiplexer channel without interfering with other I/O operations in progress on the channel.
HALT DEVICE should always be used instead of HALT I/O to stop an I/O operation on a 2880 Block Multiplexer channel.
The 2870 Multiplexer can control concurrent execution of 192 slow-speed to medium-slow-speed devices, one with each of its 192 subchannels.
Depending on the channel priority assigned, the 2870 can support a data rate of up to 110 KB. The maximum aggregate byte data rate of the 2870 Multiplexer subchannels is reduced
by
the inclusion of one or more selector subcbannels, each of which can have up to 16 I/Odevices attached. Each of the first three selector subchannels included can operate at a 180 KB rate, can handle one burst operation at a time, and reduces the aggregate byte rate of the multiplexer interface by 10 KB to 25 KB depending on the priority of the 2870 and the total I/O configuration. The fourth selector subchannel can operate at a rate of 100 KB and further reduces the maximum aggregate rate of the multiplexer subchannels by 14 KB. If two 2870 Multiplexer Channels are installed, the second 2870 can have only two selector subchannels.
The 2860 and 2880 channels permit attachment of a wide variety of high-speed I/O devices to the Model 165. The 2860 Selector Channel handles data rates of up to 1.3 megabytes, while the 2880 Block Multiplexer can handle a 1.5-megabyte rate, which permits attachment of the 2305 Model 2 facility. The Two-Byte Interface optional feature can be installed on a 2880 to double its data transfer rate capability to 3.0 megabytes so that the 2305 Modell facility can be attached.
The Model 165 user has more flexibility than the Model 65 user when configuring channels. On a Model 165, channel address and channel priority are not related, as they are on the Model 65. Any channel address (0 through 11) can have any channel priority (1-12) assigned.
Thus, the Model 165 user can assign channel priority by channel type in order to achieve the desired aggregate channel rate and insure that the highest speed devices are assigned the highest channel priorities.
The maximum speed of an I/O configuration possible on a Model 165 with minimal overrun exposure is a function of the I/O devices used, the channel types installed, the channel priority assignments, and the types of channel programs operating concurrently at any particular instant. Examples of configurations that will operate on the Model 165 follow.
26
1. A seven-channel system including one 2870 Multiplexer and six 2860 Selector Channels with a maximum aggregate channel data rate of approximately 4.25 MB.
Channel Channel Channel I/O Data Rate
Priority Address Type Device in ME
1 1 2860 2301 Drum 1.250
2 2 2860 2301 Drum 1.250
3 0 2870 2401 Model 6 SSCl .180 2401 Model 6 SSC2 .180 2401 Model 3 SSC3 .090 2540, 1403, terminals
on MPX .020
.470
4 3 2860 2314 or 2420
Model 7 .320
5 4 2860 2314 or 2420
Model 7 .320
6 5 2860 2314 or 2420
Model 7 .320
7 6 2860 2314 or 2420
Model 7 .320
2. A seven-channel system including one 2870 Multiplexer and six 2880 Block Multiplexer channels with a maximum aggregate data rate of approximately 7.8 MB.
Channel Channel Channel I/O Data Rate
Priority Address Type Device in ME
1 1 2880 2305 Model 1 3.0
2 2 2880 2305 Model 2 1.5
3 0 2870 2401 Model 6 SSCl .180 2401 Model 6 SSC2 .180 2401 Model 3 SSC3 .090 2401 Model 3 SSC4 .090 Unit record on MPX .023
.560
4 3 2880 3330 facility .806
5 4 2880 3330 facility .806
6 5 2880 3330 facility .806
7 6 2880 2314 or 2420
Model 7 .320
3. A seven-channel system including two 2870 Multiplexer and five 2880 Block Multiplexer channels with maximum aggregate data rate of approximately 6.8 MB.
Channel Channel Channel I/O Data Rate
Priority Address Type Device in MB
1 1 2880 2305 Model 1 3.0
2 0 2870 2401 Model 6 SSC1 .180 2401 Model 6 SSC2 .180 2401 Model 6 SSC3 .180 2401 Model 3 SSC4 .090 MPX .027
.660 3 2 2870 2401 Model 6 SSCl .180
2401 Model 6 SSC2 .180 MPX .040
.400
4 3 2880 3330 facility .806
5 4 2880 3330 facility .806
6 5 2880 3330 facility .806
7 6 2880 2314 or 2420
Model 7 .320
4. A twelve-channel system including one 2870 Multiplexer and eleven 2880 Block Multiplexer channels with a maximum aggregate data rate of approximately 9.4 MB.
Channel Channel Channel I/O Data Rate
Priority Address Type Device in MB
1 8 2880 2305 Model 1 3.0
2 9 2880 2305 Model 2 1.5
3 0 2870 Multiplexer aggregate .560
4 10 2880 3330 facility .806
5 11 2880 3330 facility .806
6 1 2880 3330 facility .806
7 5 2880 2314 or 2420
Model 7 .320
8 3 2880 2314 or 2420
Model 7 .320
9 4 2880 2314 or 2420
Model 7 .320
10 2 2880 2314 or 2420
Model 7 .320
11 6 2880 2314 or 2420
Model 7 .320
12 7 2880 2314 or 2420
Model 7 .320
The Model 165 with a 2 microsecond processor storage is able to achieve higher aggregate data rates than the Model 65 with a .750
microsecond main storage because Model 165 operations have been designed to optimize the use of four-way doubleword interleaving by use of more I/O buffering. Additional channel buffers are provided in the Model 165 CPU and the 2880 channel, which permit effective use of interleaving during I/O operations and help prevent data overrun when peak activity occurs.
The storage control unit contains four dedicated 8-byte buffers for each channel that are assigned when the channel is installed.
In addition, each 2860 Selector Channel contains two 8-byte buffers, and a 2880 Block Multiplexer·Channel contains two 16-byte buffers or four 16-byte buffers depending on its maximum rate, 1.5 MB or 3 MB.
The use of I/O buffers in the SCU allows channel requests to be made to processor storage concurrently with other channel or CPU
requests when requests are for different logical memories. Additional internal buffering in the 2880 channel allows i t to withstand longer wait times for requested logical memories and thus reduces channel overrun exposure.
The channel buffering scheme implemented in the Model 165 is most efficient for 2880 channels. Use is made of all four buffers available per channel, while only two buffers can be used for 2860 channels.
This scheme supports overlapped processor storage requests from the same 2880 channel so that at any given channel priority position, a 2880 can sustain a higher data rate than a 2860.
A 2301 drum connected to a 2860 Selector Channel must be placed in the highest or second highest channel priority position on a Model 165. Channel address 1 or 2 must be used. For most efficient operation of 2301 drums, they should be attached to a Model 165 via a 2880
channel, since the 2301 causes much less CPU interference during data transfer operations when connected to a 2880, rather than to a 2860.
In contrast to the Model 165, the Model 65 does not contain
additional buffering in its CPU and because of timing considerations cannot utilize the two-way interleaving capability of its main storage for I/O operations. Thus, in a Model 65, without the use of buffering in the SCU, the memory bus is busy for an average of 1.1 microseconds when storing one doubleword from a 2860 channel buffer. In a Model 165, with no interference, four doublewords from channel buffers in the
SCU can be placed in processor storage in 2 microseconds (one doubleword in each logical memory).
Comprehensive error checking has been incorporated in the basic design of the channel hardware. Checking is performed on the control logic in most areas and standard parity checking is done on the data flow. Improved error recovery hardware has also been included
(discussed fully in the RAS section).
The Channel-to-Channel Adapter feature available for the Model 65, which permits two System/360 channels to be interconnected, is also an optional feature for the Model 165. The Channel-to-Channel Adapter itself cannot be installed on a 2880 or a 2870 channel; however, a
2880 or a 2870 can be connected to an adapter installed on another channel. Thus, a 2880 or a 2870 can be interconnected to a 2860 channel, a Model 155 channel, a Model 50 channel, etc., that has the Channel-to-Channel Adapter attached.
THE 2880 BLOCK MULTIPLEXER CHANNEL
The 2880 can operate either as a selector or a block multiplexer channel. The setting of a channel mode bit in a control register determines the mode in which 2880 channels operate. The mode bit is set to selector mode at IPL and on system reset and can be altered by programming at any time. When a START I/O instruction is issued to a 2880, the setting of the channel mode bit determines the mode in which the addressed subchannel will operate.
The new START I/O FAST RELEASE instruction can be used with 2880 Block Multiplexer channels. This instruction differs from a START I/O in that START I/O FAST RELEASE permits the CPU to execute the next sequential instruction sooner. That is, if the addressed 2880 is not busy when START I/O FAST RELEASE is issued, the assumption is made that the I/O operation can be started and the CPU is not held up
awaiting a response from the device'S control unit. If i t is determined
28
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