SMOOTH-SCROLL MECHANISMS The Am8052 provides very powerful smooth-scroll

capability with minimum interaction by the CPU.

Window(s) or background can be smooth-scrolled either up or down at a rate that is programmable via the scroll parl;imeters field in the Main Definition Block. Since the CRTC is designed towork with a linked-list structure, some' precautions should be taken when relinking the text after each scrolled row.

General Smooth-Scrolling Rules

Either windows or background can be scrolled at one time; they cannot be scrolled at the same time.

When a window splitting the screen vertically (sharing the row buffer with background ,characters) is intended to be smooth-scrolled, then all of its rows must have the same total scan line counts (TSLC).

Double Buffering Technique

Smooth-scrolling operation is achieved by moving the appropriate data up or down on a scan line made. This relink serves to push the disappearing row off the screen or to link a new row onto the top of the screen.

In order to maintain asniooth relink transaction and allow for CPU time constraints, the Am8052 controls the relink timing through interrupts and double buffering' of pointer register. As soon as the CRTC has begun smooth-scrolling a character row, it generates an interrupt. The CPU which maintains the linked-lists responds by writing to

"Top of Page (Window) Soft" a pointer value that provides the correct linked-list for the display after , it has completed the scroll of the current row. The the CPU to relink and respond to the interrupt.

According to the preceding, when the user wants to smooth~scroll a portion of the, display (background or window), he should define two Main/Window Definition Blocks, and flip between those two blocks each time a smooth-scroll interrupt occurs. This technique allows the user to execute the link modifications on the unused definition block while the other is being processed bytheCRTC. Page/Window Register (Hard Register) used by theCRTC to fetch the Main/Window Definition Block. In fact, the transfer between this temporary register to the actual register takes place according to ,the smooth-scroll algorithm internal to the CRTC. Therefore, if the smooth-scroll process has not been enabled, writing to Top of PageIWindow Soft does not change anything in the link architecture and this register should be used only if smooth-scroll operation is (or will be) performed.

If the user wants to. change the link in a

Background scrolling and. ,Up/Down scrolling directions. Additionally, when scrolling 'windows, the Smooth-Scroll Window bit (SCW) in the corresponding Window Definition Blocks must be set. All windows which have SCW set are.scrolled simultaneously. Windows which have SCW reset remain steady.

Smooth scrolling is stopped by resetting the enable bit (SSE-Bit) in the Main Definition Block.

When the backgrC'und is scrolled only Top Of Page Soft needs to be updated; loading Top of Window Soft has no effect. Similarly, when ' scrolling windows only Top Of Window Soft is relevant.

Scroll Down

The Top of PageIWindow Hard Register links to the MainlWindow Definition Block of the currently displayed text. When a down scroll is initiated, the current text is moved down a fraction of a row. The empty space at the top of the screen is filled with a fraction of the scrolled-in row. Therefore, the CRTC has to know the pointer to the new Main/Window Definition Block before it can start scrolling. The pOinter is loaded into the Top of Page/Window Soft Register.

The programming sequence shown in Figure 2.42 refers to both scrolling background or windows.

CRTC REGISTERS

MOBs, WDSs

11) 12)

The example shows two rows scrolling in a background or window consisting of a total of four rows. When scrolling the background the TOP Soft Register is reloaded and two Main Definition Blocks are used to implement the "Double Buffer"

technique. If a window is scrolled, the TOW Soft Register and two. Window Definition Blocks are involved. The numbers in the programming sequence below correspond to Figure 2.42.

1. The CRT system displays a steady screen. The TOP/TOW Hard Register links to a MDBIWDB with smooth-scroll disabled. The smooth-scroll process is inniated from this steady state.

13)

SIP=O .--_15_) - - . ~T

2ND SCROLLED IN ROW

03901A-42

RCBs.

WRCSs

1ST SCROLLED IN ROW

ORIGINAL 1ST ROW

ORIGINAL 2ND Rbw

L

ORIGINAL 3RD ROW

ORIGINAL 4TH ROW

Figure 2-42 Scroll Down Sequence

2-47

I

AFTER SCROLLING DOWN TWO ROWS 15)

I I -.J

BEFORE SCROLLING 11)

2. The CPU prepares another MOB/WOB with smooth-scroll enabled. This MOBIWOB con-tains a pointer to the ROBIWRCB for the scrolled-in row which in turn points onfo the first row currently displayed on the. screen. The CPU loads the pointer to this MOBIWOB into

~oprrow Soft Register.

3. The CPU then enables smooth-scrolling by setting the smooth- scroll bit in the MOBIWOB described in Step 1. The CRTC detects this change when it fetches this block during the next vertical retrace period. The first frame after this change still reflects the same unscrolled display. Scrolling begins with the following frame. If the TOprrOW Soft Register was not initialized, the start of scrolling waits for the initialization. At this time the CRTC transfers the contents of the TOprrOW Soft Register to the TOprrOW Hard Register to allow scrolling to the new row. It issues an interrupt on smooth-scroll event to notify the CPU that the TOprrOW Soft Register can be updated. The update can take place at any time until the new row is entirely scrolled-in. If the update was not performed at that time, the displayed text scrolls up (hard-scroll) one row and this same.

row is smooth-scrolled in again.

4. The TOprrOW Soft Register is relinked to the tvlOBIWOB pointing to the ROB/WRCB of the next row to be scrolled-in. If only one row should be scrolled, Step 4 is left out. For scrolling "n" rows, Step 4 is repeated after each interrupt issued by the CRTC "n-1" times.

5. To stop the smooth-scroll process, the new pointer in the TOP/TOW Soft Register points to a copy of the previous MOBIWOB in which- the (Smooth Scroll in Progress) being reset.

Scroll Up

The numbers in the progralnmingsequence below correspond to Figure 2.43.

1. The TOprrOW Hard Register links to the MOBIWOB of the currently displayed text.

. Smooth-scroll is disabled.

2. The scroll process is initiated by enabling smooth-scrolling in the MOBIWOB. The TOprrOW Soft Register does not need to be

loaded at that time. The last row displayed links to the row to .be scrolled-in. ,The CRTC detects the change of the scroll enable bit when it fetches the block during the next vertical retrace· period. After it has started smooth-scrollil')g it issues an interrupt on smooth-scroll event to make the CPU update the TOprrOW TOprrOW Soft Register points toa MOBIWOB with scroll disabled ( S S E = O ) . '

Smooth Scroll in Progress B1t (SIP· Bit) The SIP-bit is a status bit in the'Mode Register 2 indicating to the CPU thai the CRTC is actually scrolling either window or background while the SSE bit (Smooth-Scroll Enable) is set. The.SIP bit is set as soon as the CRTC has loaded the Main Definition Block with SSE=1. Nevertheless, once the CPU resets SSE to "0," the CRTC waits until the entire smooth-scroll is finished before resetting SIP to "0." Furthermore, when using vectored interrupt, the SIP bit appears in Bit 1 of the interrupt vector and, therefore, allows the user the ability to vector to two different programs depending on the status of smooth-scroll without polling the SI P bit.

The CRTC scans the SSE-bit in the Main Definition Block only at the top of the frame (not scrolling) and after transferring TOPITOW soft register to TOprrOW hard register (previous frame was smooth scrolled). After scanning the MOB, and a relink took place; and the previous frame was scrolled, then the CRTC sets the interrupt pending bit for smooth scroll. At that time the SIP-bit reflects exactly the state of the SSE-bit in the scanned MOB.

If at that timeSSE=1 the CRTC issues an interrupt with SIP=1 asking the host CPU to load a new pOinter into the soft register; a pointer required for the subsequent relink. In this case scrolling continues.

If at that time SSE=O the CRTC issues an interrupt with SIP=O notifying the host CPU that scrolling has been terminated.

·Smooth·Scroll Parameters

IUSS. Interrupt Under Service for Smooth·Scroll operation (Bit 2 in Mode Register 2) is set either by a hardware interrupt acknowledge (INTACK Low) or bya software interrupt acknowledge (host CPU sets IUSS).

IES.. Interrupt EnableSmooth·Scroll Bit 1 in Mode Register 2. enables smooth scroll interrupts.

Alternatively, the host CPU can poll the interrupt pending bit to perform the smooth scroll relinks.

CRTC REGISTERS

MOBs, WOBs

(1) (2)

This bit can only be set and reset by the hqst CPU.

IPS. Interrupt Pending for Smooth·Scroll event.

Bit 0 in Mode Register 2. This bit indicates that the smooth scroll logic requires service by the host CPU. This bit is set by the CRTC or the CPU, and reset only by the CPU. It it independent of the state of IES.

SIP. Scroll in Progress, Bit 8 in Mode Register 2.

. Set and reset by the CRTC.

SIP=l SIP=O

r--_(4~) --.~T

BEFORE SCROLLING (1)

ORIGINAL 1ST ROW

03901A-43

RCBs, WRCBs

L

ORIGINAL 2ND ROW

ORIGINAL 3RO ROW

ORIGINAL 4TH ROW

1ST SCROLLED IN ROW

Figure 2·43 Scroll Up SeqLlence

2·49

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AFTER SCROLLING UP TWO ROWS (4)

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2.9 SYNCHRONIZATION

The CRTC has two built·in synchronization mechanisms: External SYNC (ESYNC) qnd Reset for Test (RSn). These mechanisms are activated by applying Signals to the synchronization input pins (ESYNC and RSn). The, ESYNC input synchronizes the CRTC to an external frame . frequency. In most applications this input locks the vertical timing to the ~ower-line frequency to avoid screen swimming. RSTT synchronizes multiple CRT controllers.

Multiple CRT Controller Synchronization The Reset for Test (RSTT) input synchronizes two or more CRTCs. This synchronization sequence is executed only upon system initialization. Figure 2.44 shows the timing diagram. RSn can synchroni?e multiple CRTCs only once after power-on,because applying RSn would corrupt the display. It cannot be used to synololronize multiple CRTCs on a frame basis. This means, that all CRTCs have to programmed in a way that they operate synchronously forever (e.g. same clock and same timing parameters).' The sequence of operation for RSn is:

Reset all CRTC's by pulling Reset (RST) Low for at least five clock cycles (CLK1 or CLK2, whichever is slower).

After RST becomes inactive, initialize all CRTC registers including MO,de Register 1 and 2 with DE=O.

Activate' RSn' synchronous to CLK1 or CLK₂ depending on the CLK1/2 bit in Mode Register 1.

It must be synchronous to the clock determining the frame timing. It must meet the set-up time ts to

avoid metastable problems.

Reload Mode Register 1 and 2 .. Set DE=1 (Mode Register 1 ).

Deactivate RSn synchronous to CLK1 or CLK2.

RSn must be active for a minimum of five clock cycles and its rising'edge must meet the hold time requirement. The rising edge of RSTT triggers all CRTC's to start display synchronously. Detailed ResetforTestTiming is shown in Figure 2.44.

External Sync Operation

The ESYNC' input allows synchronization of the CRT display vertical frame rate to the power line frequency to eliminate waviness and other effects.

The ES bit in Mode Register 1 defines whether ESYNC controls the Vertical Sync rate.

ESYNC is recognized by the CRTC for every field or frame. It causes the VSYNC signalto become active at the occurrence of HSYNC. In non-interlaced mode, VSYNC becomes active at the first rising edge of HSYNC following ESYNC's risihg edge (Figure 2.46). In interlaced mode, VSYNC ,comes active at the next HSYNC active when in the even frame, or in the middle between two HSYNC's in the odd frame (Figure 2.47).

The VSYNC and HSYNC are inactive (BLANK is active) before, during, and after reset. When the display is enabled via mode bit DE, HSYNC output becomes active, while VSYNC waits for ESYNC active. The display is delayed up to one ESYNC period.

ESYNC cannot be used to synchronize multiple CRTCs, since it synchronizes only VSYNC, but not

03901A-44

Figure 2-44 Reset for Test Timing

HSYNC. Only RSn can synchronize multiple CRTCs.

2.10 RFI and INTERLACED VIDEO

There are two types of interlace, Repeat Fielc;t

Interlac~ (RFI) and Interlaced Video (IV). Both types use the same vertical and horizontal timing as described in the Vertical and Horizontal Timing Section. Both schemes offset the vertical position of the scan lines of the odd numbered fields so that they are physically interleaved with the scan lines of the even fields; For RFI, the same video information is displayed on both odd and even fields. The slight offset of the odd field eliminates the horizontal stripes that sometimes occur between scan lines on non-interlaced displays.

(See Figure 2.48)

Interlaced Video is used to increase the amount of information displayed on a monitor . without increasing the horizontal or vertical scan rates. IV takes advantage of the odd field scan line offset by displaying half the video in the even field (alternating lines) and half in the odd field. The effect is to essentially double the vertical character density with respect to RFI or non-interlaced video.

One problem with IV is the potential imbalance of

ClK1,2(1)

CRT beam current between the odd and even fields and the resulting loss of perfect video interleave. This. imbalance is greatest if the character rows consist of an even number of scan lines (adding up the scan lines in the even field and the odd field).

Restrictions for Interlace Video

The restrictions mentioned below apply only to Interlace Video. They do not apply to RFI or non-interlace video;

If smooth scrolling is disabled, any mixture of background and windows can be displayed, as long as windows are horizontally separated by three or more character rows (not scan lines).

Windows should not overlap horizontally.

The Am8052 does not support split-screen smooth-scrolling in Video Interlace mode .. Also, in Video Interlace mode, a screen containing only background and no windows can only be smooth- . scrolled if all rows have an even scan count (TSLC even) and the number of scan lines scrolled per frame is also even (scroll rates: 2, 4, 6, 8 scan lineslframe. No scrolling restriction applies to non-interlace or RFI video. .

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VSYNC

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(1) CLK1 OR CLK2 DEPEND)NG ON CLK1/2 IN MODE REGISTER 1 (2) BLANK. HBLANK + VBLANK

0390iA·43

Figure 2-45 Detailed Reset for Test Timing Diagram

2-51

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~---,. I'i"""""

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:::::_~_n __ .~_,~._'...1=~

W'''_ ~~ ~

Figure 2-46 Non-Interlaced ESYNC Operation

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JLJl..-.

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Figure 2-47 Interlaced ESYNC Operation

5' ^pt-K + SKEW (1) 5 CLK t SKEW (2)

If ROW ATTRIBUTES'\!

12CLK, + SKEW (2)

(1) 'eLK IS CLK, OR CLK •• DEPENDING ON PRoGRAMMING OF MODE REGISTER 1 (0,.). SKEWISCLK, ORCLK. CYCLES;

vALUE SRECIFIED IN MODE,REGISTER 1 (Dg,.D.) . (2) SKEW IS CLK~ CYCLES; VALUE SPECIFIED IN MOOE

REGISTER1 (D • • P. )

Figure 2-48 Row Attribute Timing

03901A-45 .

03901A-46

05098B 2·48

RFI INTERLACED VIDEO NON·INTERLACED VIDEO

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Figure 2·49 Scan line Addressing

'2·53 .

(

CHAPTER 3

Dans le document Controller The Am8052 (Page 61-70)