Once the CRTC has been initialized and the various registers programmed to meet the application's needs, the CRTC is responsible for initiating System Bus Requests to fetch Control Data and Display Data from memory and to transfer them into its on-board registers and row buffers, respectively. The CRTC requests the bus after the DE-btt in Mode Register 1 has been set to a "1."
DMA Signals and Protocol
Before the CRTC can, perform a DMA operation, it must gain control of the System Bus. The BRO, BAI and BAO interface pins constitute the basic interface between the CRTC and other devices capable of .bus arbitration (e.g. microprocessors and other DMA devices). Whenever the CRTC requests bus control, the operation is executed according to the flowchart in Figure 2.23. The DMA sequence can described as the foliowinQ:
1. If the CRTC needs to perform a DMA access, it triggers the bus request operation.
2. First, it checks whether the bus is being used
~nother peripheral device by polling the BRO line until it is High. Then, it waits for the CPU to gain bus control.Tt.lis is indicated through the daisy-chain (BAI=High).
This is a "don't care" since HOS=O. (HSYNC
selected) 3. At that time the bus is under control of the
2-23
DMA ACTIVATED
START OF BUS REQUEST OPERATION
POLLING FOR BUS
RELEASE FROM BUS·MASTER (IF PRESENT) AND FOR BUS RELEASE ACKNOWLEDGE FROM CPU •
ACTIVATING BUS REQUEST LINE AND DAISY CHAIN LOCK
WAITING FOR BUS REQUEST ACKNOWLEDGE FROM CPU
DMA TRANSFER OPERATION
DMA TRANSFER INTERRUPTION?
BUS RELEASE AT END OF DMA TRANSFER
TEMPORARY BUS RELEASE
Figure 2-23 DMA Bus Request Flow Chart
2
4
6
8
03901A-25
CPU, and the CRTC can issue its request by pulling BRQ Low. It also inhibits Bus Acknowledge from propagating to lower priority devicesJj!!Jhe lower part of the daisy-chain) by pulling BAO Hig/1; this avoids granting the Bus to lower priority devices which may have issued BRQ at the same time as the CRTC.
4. Before initiating gny DMA transfer, the CRTC waits for bus re9lJ§st acknowledge from the CPU by polling its BAI input. .
5. The CRTC now acts as Bus Master and performs the required transfers.
6. The eRTC DMA transfer can be temporarily interrupted by removing Bus Acknowledge In (BAI=High)-external bus preemption. The CRTC requires that BAI is active for a minimum of four clocks. If the CRTC is preempted within the first four clocks, the CRTC might not detect the bus acknowledge causing the CRTC to keep waiting for BAI Low. The result is that the
bu~ arbitration locks up. To overcome this lock condition either the minimum width of BAI must be guaranteed or the external arbiter must be able to recover from this lock condition (detect of lock, then temporary release the preempting signal).
7 .. The CRTC terminates the transfer when it has filled the internal row buffers or when the burst count reaches zero. The bus is released (BRQ=Hi9!!L aM. bus acknowledge ripples through (BAO=BAI). Then either the CPU or a lower priority device on the daisy chain can gain
5V
control of the bus. ----.JJ:le lower priority device might have pulled BRQ Low concurrently with the CRTC and is waiting for BAI=Low to start its activity.
8. The CRTLDMA transfer is interrupted by removing BAI. The CRTC finishes the current bus cycle and~eases the b~ for three system clocks (BRQ=High, BAO=BAI). Then it tries to resume DMA activity and continues DMA operations and burst count from where it was interrupted.
Buffering BRO
When BRQ needs to be buffered (for example, to drive a system backplane),
a
speCific bidirectional interface buffer must be used. Such an interface and its implementation is described below:Detail "A" in Figure 2.24 shows the BRQ buffer logic .. Note that the "buffer" and the "OR gate" are both open collector (OC) devices. When the backplane BRQ is High, and no DMA device requested the bus, then all BAI's and BAO'S are High, hence X3 and X2 are High and X1 is driven High.
If device X requests the bus, it locks BAO High arid pulls X1 Low to initiate a bus request, which in turn pulls X3 Low since X2 is High (BAO=High). The detail "A" logic is then locked into this state through the open collector buffer, as the CPU and the other detail "A" interfaces on the bus. All these interfaces are locked the same' way as the
DETAIL "A"
BRQI.-~~---~---~~~~
CPU.
03901A-26
• CRTC ' DEVICE X
DTC DTC
DEVICEY DEVICEZ
Figure2-24 System with Multiple DMA Devices
2-25
requestir19 one. A few, cycles later, the CPU acknowledges the bus request by pulling BUSACK Low, the CRlC (device X) then executes its transfers. When the CRTe finishes its trans~
it releases BRQ and relinks its BAI input to BAO 'output, hence driving BAO Low. The Low propagates through the daisy-chain, and as lohg al:) one of the:BAO is High, the backplane BRO line and the devices BRO signals will be held Low due to detail "A" logic structure.
On~e
all theBAO'~
have gone High, the backplane BRO goes High, and the CPU gains control over the bus.DMA Transfer Operation
The DMA transfer itself consists of data moves from memory into the CRTC, controlled by the CRTC's DMA unit.
If a control block is fetched, the words loaded are steered toward the internal control registers. If display data (characters or attributes) are fetched from memory, it is steered toward an internal row buffer.
In both cases the CRTC must:
1. Output the address 01 the data iocation.
CLK1
ADo-AD,.
R/Vi
2. Sample the WAIT input and Wetch the read cycle if needed. WAIT is sampled only at the falling edge of the system clock in T2 of a Bus Master Read cycle.
3. Read the data and transfer it to the proper destination (buffer or internal register).
The Am8052 can address up to 16-Mbyte addresses as 256 pages of 64K bytes each. The upper address is updated on a qemand basis, as outlined below:
There is a Lipper address change between the previous fetch cycle and the current one, or this 'is the first fetch of a new frame. In either case, succeeding read cycles are preceded by a single write cycle to latch the new upper address address. (See Figure 2.25)
There is no upper address change since the previous fetch cycle and it is not the first fetch of a new frame. In this case t~e succeeding fetches are not preceded by a upper address write cycle.
A new burst does not necessarily begin with a page address update.
DMA Read and Write Operations
The start 01 a DMA ,cycle is initiated by AS being
i - - - D M A READ CYCLE WITH PAGE C H A N G E - - - i
03901A-2'i Figure 2-25 DMA Transfer Operation
driven Low, which indicates a valid address on the ADo-AD15 address/data lines. At that time DTEN is also driven Low and allows the valid address to be buffered on the system bus through external buffers. The valid address may be latched on the system bus on the rising edge of AS,
During the first portion of a DMA read cycle with a write cycle. The next three clock cycles represent a normal DMA read cycle.
During T2 the CRTC ceases driving the ADo-A015 bus with. the address information, and DTEN goes inactive (HIGH). OS is driven Low as an indication to the memory system that it may drive the bus with the read data. Half of a clock cycle later, OREN is hold time required by the CRTC is satisfied.
Wait Operation
During T2 of the read cycle, the WAIT signal is sampled by the falling edge of CLK1' If Low, the cycle is stretched by one CLI(1 cycle. However, the WAIT input can be operate~as a READY input, by taking Low as the default level. In both- cases, the input signal must satisfy the setup and hold time requirements ql the CRTC, to avoid metastable conditions (see Section 6).
The CRTC also has a software Wait state capability:
zero, one or two wait states can be ~pecified in Mode Register 1 and are automatically inserted in each Bus Master Read cycle independently of the WAIT input line. '
When both hardware and software Wait states are . requested, they occur consecutively and not concurrently: The hardware Wait States are honored first, immediately followed by software wait states if so programmed.
Idle DMA Cycles
An I,dle DMA cycle is a bus cycle (three clocks)
during which the CRTC executes internal operations (e.g., row linkage and window overlay).
Since Idle DMA cycles are single bus cycles, the CRTC does not relea"se the bus; otherwise, bus overhead, would be increased. The CRTC releases the bus (burst of Idle DMA Cycles) only if a window or the background row needs to be filled with Fill Code characters.
Each DMA burst executes in the following sequence:
1. The CRTC asserts BRO to arbitrate the bus.
2. The CRTC waits for BAI to be asserted by the external bus arbiter (usually a CPU).
'3. BAI is sampled with the ne~t rising edge of CLK1' If the set-up time (parameter 75) is not satisfied, the CRTC may perhaps not catch BAI with that edge, but, definitely catches it with. the next edge (metastable conditions cannot occur).
4. Then BAI is internally synchronized to T2 of the running state machine. After synchronization the CRTC executes the first DMA cycle, which
Table of Idle DMA Cycles:
The table below lists conditions were the CRTC inserts Idle DMA cycles (this list might not be complete).
Event # of Idle
DMA Cycles Begining of DMA burst if previous burst
was preempted or counted out 0 Begining of the first burst of a frame 1 Begining of first burst for a new row 2 Loading the Window Definition Block 1 Loading a Row Redefinition Block 1 Loading a Window Row Control Block 1
End of a row (background) 1
(window) 2
End of preempted burst 0
Fill Code segment (segment with 1 character pointer equal zero)
Window segment filled with Fill Code 3clks/2char
2-27
DMA Burst Control
Ouring DMA action, ,the CPU IS denied aCCElSs,to the bus and therefore cannot execute programs~
. This situation can lead to problems in the interrupt response Jime of the CPU, since the CPU can only re.c6grii~e 'and service an interrupt re~uest while in ' control of the bus. Note that at the beginning of everY frame; immediately after the vertical bla:nking Interval, the CRTC tries to request the bus.
" . ' ' I
To allow the CPU cbntrol of the bus within certain limits,a BurSt Register is ptovided inside the CRTC and is programmable by the CPU. This Burst Regis~er sPecifies a time slot during whiCh the CRTC is allowed to request the bus; Both the time slot duration arid its cycle time are programmable.
Forfurtherinformation, refer to Section 2.3.