Repeat Problem 3.14 by using NORJINV logic. Assume that all inputs arrive from positive logic sources

= iia + iib

3.15 Repeat Problem 3.14 by using NORJINV logic. Assume that all inputs arrive from positive logic sources

3.16 Repeat Problem 3.14 by using AND/ORJINV logic. Assume that all inputs arrive from positive logic sources.

3.17 Use three NOR gates (nothing else) to implement the function Y(H) below ex-actly as written. Assume the inputs arrive as follow: A(H), B(H), C(H), D(L), and E(L).

Y(H) [(AD) . (B

+

^E)](H)

3.18 Use three NAND gates (nothing else) to implement the function Z(H) below ex-actly as written. Assume the inputs arrive as follow: A(H), B(H), C(H), D(L), and E(L).

Z(H)

=

^[(A

+

^D)

+

(BC E)](H)

3.19 Name the gates used in each of the logic circuits shown in Fig. P3.3 and give the mixed logic expression at each node in mixed logic notation. Use Figs. 3.20, 3.23, and 3.24 as a guide if needed.

3.20 The CMOS circuits in Fig. P3.4 perform specific logic functions. Construct the physi-cal and mixed logic truth tables for each circuit, indicate what logic function it performs and give its two conjugate logic circuit symbols. Note that

B

is the inverse voltage of B.

3.21 Use two NOR gates and one XOR gate (nothing else) to implement the function Y (H) below exactly as written. Assume the inputs arrive as A(H), B(H), C(H), D(L), and E(L).

Y(H) = r(A $ D) . (B

+

^E)](H)

3.22 Use three NAND gates, one EQV gate, and one inverter (nothing else) to implement the function G(H) below exactly as written. Assume the inputs all arrive from positive

PROBLEMS

A(H)~l

^X(l) D(H)

3 Z(H)

8(H) 2

C(H) Y(H)

(a)

125

Y(H) C(H)

(b)

A( H) -::-_-1 8(H)

C ( H ) - - - I

F(L)

(e) O(l) _(d)

FIGURE P3.3

logic sources.

G(H) = [(X Y) (l)

Z +

^XYZ](H)

3.23 Use three NAND gates and two EQV gates (nothing else) to implement the func-tion F(H) below exactly as written. Assume the inputs arrive as W(L), X(L), Y(H), and Z(H).

F(H) = [(W (l) Y) (l)

CXZ) +

WY](H)

3.24 Unused inputs must not be left dangling. Instead, they must be tied to other inputs, or be connected to HV or LV depending on the logic operations involved. Implement the following functions with the logic indicated.

(a) A four-input NOR gate performing the (AB)(H) operation with inputs A(L) and B(H).

(b) A three-input NAND gate performing the X(H) -* X(L) logic level conversion operation.

(d) A four-input AND gate performing the (.4

+

^B)(L)operation with inputs A(H) and B(L).

3.25 Construct the truth table and the mixed logic waveforms for the functions below by using a binary input sequence in alphabetical order, all inputs active high. Use Ta-ble 2.1 in Section 2.3 if needed, and follow the format of Fig. 3.32 in constructing the waveforms. Do not take into account the propagation delays through gates and inverters.

V(L)

126 CHAPTER 3/ BACKGROUND FOR DIGITAL DESIGN

B - - - '

(a)

B -..--+---.

B -~-+---'

(e) FIGURE P3.4

(a) Function Z(H) in Fig. P3.3a.

(b) Function G(H) in Problem 3.22.

A r---+- Z

(b)

3.26 Reduce the following expressions to their simplest form and name the Boolean laws used in each step. (Note: Follow the procedure of Examples 3.6 in Section 3.12.)

(a) ab(c

+ h) + ah

(b) (X

+

Y)(XZ

+

Y) (Hint: First use the distributive law.) (c) A

+

(d) (x

+

^y)(x

+

^z)[y(x

+

^y]

(e) AB

+

Ac D

+

PROBLEMS 127

3.27 Reduce the following expressions to their simplest form, but do not name the Boolean laws used in each step.

(a)

A +

^ABC

+ A +

(b) (aed

+

ad)(ad

+

cd)

(c) (WX+Y+W)(WX+Y+WX) (d) (x

+

y)(i

+

z)(y

+

(e) (A

+

BC)(AB

+

ABC) (Hint: Simplify under short complementation bars first.) (f) ii

+

a(h

+

be)

+

^{c) .}abed

(g) (A

+

D)(,.1

+

D)(,.1

+

D) (Hint: First use consensus.) 3.28 Reduce the following expressions to their simplest form and name the Boolean laws

used in each step.

(a) (a EB b

+

b)(a

+

b) (b) (XY) EB (X

+

(d) [(X

+

^Y)0 (X

+

^Z)]

+

(e) [(A

+

^{B) .}^C]EEl [A

+

^AC] (Hint: Find a way to use Corollary II.)

3.29 Reduce the following expressions to their simplest form, but do not name the Boolean laws used in each step.

(a)

A +

A EB B

+

,.1B

(b) (05

+

[S EB (ST)]}(H) = [?](L) (c) (X

+

^Y)0 (X EB Y)

(d) (a 0 b) EB (ah) (e) (i

+

^y)(xEB y

+

^y)

(f) [1 EEl (1

+

oJ)

+

1 0 O](H) = [?](L)

3.30 Use the laws of Boolean algebra, including the XOR laws, identities, and corollaries given by Eqs. (3.17) through (3.33), to prove whether the following equations are true (T) or false (F). Do not name the laws used.

(a) X 0 (X

+

Y) = XY

(b) ab(h

+

be)

+

abed = be (c)

A

EB B EB (A B) = ,.1B

(d) X EB (XY)

=

+

(X 0 Y) (e) f(AB)(A 0 B)](L) = ,.1B(H)

(f) AXY

+

^AXY

+

^,.1Y

=

^(AX)EB Y (Hint: First apply Corollary I.)

3.31 Use whatever conjugate gate fOlms are necessary to obtain a gate-minimum imple-mentation of the following functions exactly as written (do not alter the functions):

(a) F(H) = ([A EB B] . [(BC) 0 D]}(H) with inputs as A(H), B(H), C(L), and D(L).

(b) K(L)

=

^[AEEl C EEl (BD) EEl (,.1BCD)](L) with inputs from negative logic sources.

D(H)

128 CHAPTER 3/ BACKGROUND FOR DIGITAL DESIGN

Oil) A(H)

B( H) -+--"--_._-1

A(H)~

_Y(l)- ₁

Z _T

B(H) X(l)

(a) (b)

A(H) B(l) C(H) Z

A(H) B(H)

C(l)

(e) FIGURE P3.S

3.32 Use NORIXORJINV logic to implement the function below exactly as written by using the fewest number of gates and inverters possible, assuming the inputs A and B arrive active low and inputs X and Y arrive active high.

Z(H)

=

^{[X0 (A

+

Y)] . B}(H)

3.33 A room has two doors and a light that is controlled by three switches, A, B, and C.

There is a switch beside each door and a third switch in another room. The light is turned on (LTON) any time an odd number of switches are closed (active). Find the function LTON(H) and implement it with a gate-minimum circuit. Assume that the inputs are all active high.

3.34 The logic circuits shown in Fig. P3.5 are redundant circuits, meaning that they contain more logic than is necessary to implement the output function. Identify each numbered gate and give the simplest mixed logic result at each node indicated. To do this, it will be necessary to use the various laws of Boolean algebra together with mixed logic notation.

PROBLEMS

A(Ll

B(L)--L~

A(Hl-S-~

B(H)-,---~

1-)

fiGURE P3.6

Fll)

129

tVt)D

T

I

,·Sect;"

I ~A'

^B)(AtB)

In-Section

I ~AB

^)t(AB)

..1

Ib)

3.35 By following Subsection 3.10.2. write the dual fonns for the functions y(H). G(H).

and Z(H) in Problems 3.21. 3.22. and 3.32_

3.36 Use the laws of XOR algebra and idenlities given in Eqs. (3.17) through (3.33) to reduce the folloWing function to its simplest (gate-minimum) fonn:

F=DmB~ BD$BCD$AeADeAceACDeAB.

3.37 The mixed logic circuit for the multiple gate realization of the XOR function F(L) =

(AB +

A8)(L) = (A 0 B)(L) = (A $ 8)(H) is shown in Fig. PJ.6a. together with its CMOS organization in Fig. P3.6b. It derives from the defining relations given by Eqs. (3.4) and (3.5). Construct the CMOS circuit (excluding inverters) for this function by using the proper placement of the PMOS and NMOS as indicated in Figs. 3.5 and P3.6b. Also. construct the physical and logic truth lables for this function.

3.38 The logic circuit fonhe funccion YU/) = IA(B

+

CD)J(H) is given in Fig. P3.7. (a) Assuming that inputs A. B. C. and D arrive from positive logic sources. construct

the CMOS circuit for the function y(H).

(b) Obtain the physical and positive logic truth table for this function.

3.39 Shown in Fig. P3.8 is a CMOS circuit having three inputs and one output.

FIGURE P3.7

81H) C(H)

O(H)

AIH) ~Y I H )

130 CHAPTER 3/ BACKGROUND FOR DIGITAL DESIGN

----.---CI

--...-1---...-0 z

C - - - 4 - - - 1

FIGURE P3.8

(a) Construct the physical truth table for this circuit taking into account all possible combinations of LV and HV inputs.

(b) If the inputs and outputs are all assumed to be active high, find the logic function for Z(H) and its logic circuit.

3.40 The CMOS circuit in Fig. P3.9 is an example of a gate-matrix layout. The circuit has four inputs, A. B. C. and D, and one output Z. Note that X indicates an internal connection.

(a) Construct the physical truth table for this circuit taking into account all possible combinations of LV and HV inputs.

(b) If the inputs and outputs are all assumed to be active high, find the logic function for Z(H) and construct the logic circuit for Z(H).