t he best means to achieve our stated performance goa ls. The tests and studies which we conducted and their resu l ts are described below .
• The :;:-; 1 00-m i l l iampere ( mA) peak , 7 0 - mA steady-state s i n k current Q 2 2 -bus transceivers were to be on the same substrate as complex
Excessive local ized power d issi pation With severa l design a lternatives avai lable ro us, we needed more experi mental data to determine the better alternatives . To obtai n t h is data , a Q 2 2 - bus octal transceiver test c h i p was designed , fabricated , and packaged by SEG c i rc u i t design
ers . Avai lable after seven months, this packaged octal transceiver rest c h i p was tested i n a MicroVAX I I CPU modu le and performed wel l u nder system condi t ions.
The test c h i p experimen ts showed that CMOS latch-up due to worst-case overshoots below ground d id nor occur. These res u l ts matched our test chip was shown ro be within rel iable opera
tion l i m i ts . Therefore, CQBIC power d issipation was not a concern i n terms of thermal characteris
tics of the planned packagi ng.
The tesr chip resul ts did lead to a compromise concern ing the stable voltage reference . Because of l arge variations i n CMOS process m a terials, a precision off-chip or external resistor wou ld bet
ter serve ro establish the requi red voltage than wou ld some risky process-desensitized structure
in CMOS.
Prior to these tests, we designed CQBIC to faci l itate the usc of e ither i n tegral transceivers or off-chip transceivers . Fortunately, the rest data wou ld a nswer questions about the organization of t he SjG mapping function, the data buffering
A RAM structure was first proposed to implement t he SjG mapping functional ity. The MicroVAX I I CPU design had used such a structure, with two 8K-by-8 static RAMs . This proposal , however, was rejected s i nce not a l l of t he RAM woul d tit on a project. Moreover, implementation of a portion of the RAM wou ld have i ntroduced a system soft
ware i ncompati b i lity with MicroVAX I I and cou ld be fabricated with reasonable yield . Also, a capabi l i ty to prefetch S/G map entries based on protocol . This protocol transfers data packers of eight-word b locks . With this protocol avai lable, we could design t he CQBlC tO cache the SjG map e ntries from system memory on demand and on
--- Development of the C VAX Q22- hus Interface Chip
Data Buffering
CVAX bus cyc le ti mes were targeted to be four or more ti mes greater than typical Q 2 2 -hus cycle t i mes. Abo. the CVAX bus was being designed ro support DMA mult idata transfers . This design was consistent with the Q 2 2 -bus block-mode data transfer prorocol . To bridge the bandwidth gap between the two buses and ro m i n i mize the use of CVAX bus bandwidth, data bufferi ng tech
niq ues were i nvestigated to opt i mi ze for Q 2 2 -bus block-mode throughput for read and wri te t rans
actions . These investigations resu.lted not on l y i n performance , read data prefetching was consid
ered necessary to compensate for the memory consider. We determi ned that rwo q uadword read buffers wou ld be sufficient to sustain the n:q u i recl throughput because read data is prcfetched based on expectations of the Q 2 2 bus block-mode protocol . Low latency was achieved by provid i ng a response to the Q 2 2 - bus as the first longword of the quadword read data was obta i ned from system memory .
Pipe lin ing the buffered wri te data cou ld be ach ieved with two buffers. each eight words deep. An ocraword block is the packet size of the Q 2 2 -bus block-mode protocol and is rhe max i m u m multi transfer block size o f the CVAX bus.
The conrrol logic wou ld be designed to al l ow one buffer ro be unloaded ro system memory while t he other was being h l led . The latency wou ld be better than that of the M icro VAX I I CPU mod u l e , since the CQBIC data was packed i nto fast octa
word buffers . The average throughput wou ld be sustained by t he four t i mes or greater bandwidth of the CVAX bus, as compared to the Q 2 2 -bus, by t he use of pipe l i ned data buffers.
The CQBIC buffering and transact ion opt i m i za
tions in conju nct ion wirh the CVAX CPU internal CQBIC can sustai n Q 2 2 -bus block-mode transfer write data rates of 3 .1 megabytes (MB) per sec transaction completes and whi l e dead lock situa
t ions are resolved. interface was partitioned i n to a master and a slave control ler. The S/G map cache also req u i red a CQBIC control functional i ty .
Clocking i m provements. The variable CVAX cycle t i me and four-phase overlapped clock i n g scheme cou ld
The impl icat ion of the sc lccrccJ CQBIC clock
• A longword CVAX write buffer
• Transaction part i tioned sequent ial control l ers . which are opt i m ized for Look-ahead data
ing the methods of the semicustom tool suite for logic and circu i t design . The semicusrom sche Interconnect verification and design rule c heck
i ng were completed using the tools from the cus
trol performance , cusrom programmable logic array ( Pl.A) sections were requ i red . The PLA goals were achieved. In fact , performance goals cou l d not have been ach ieved w i t hout custom scheme . Hence the .JRDC team developed i rs own extensions tO the standard ce l l l ibrary. The com latched pad transceivers, synchroni zers, PLA AND plane drivers, and PLA OR plane receivers , were designed and made avai lable ro the l ibrary .
The JRDC ream accurately modeled the chip specification . This envi ronment model was layered around the CQBIC behavioral model to