JMP I SUBRTN CIF
CHAPTER 5 INPUT/OUTPUT BUS DESCRIPTION
5.2 MULTI-LEVEL AUTOMATIC PRIORITY INTERRUPT
The KF12B Multi-Level Automatic Priority Interrupt is designed to reduce the central processor overhead during the servicing of program interrupts. It is prewired in the EP section of the PDP-12 in racks P and R and utilizes ap-proximately 55 M series modules. There are three major services provided automatically by the KFl 2B.
a. Automatic determination of device priority and vectoring of interrupt service routines.
b. Automatic saving and restoring of all major registers and machine status which include the following:
PC, AC, IF, DF, MQ, LINK, FLOW, UF, MODE and the current processor level.
c. Automatic stacking of the saved parameters permitting multiple levels of interrupts.
Storing, or stacking, of parameters is called Pushing and restoring the CP to its original status prior to an interrupt is called Popping. The CP is in the break state for the duration of each operation. It takes five break cycles for each Push and five break cycles for a Pop. This does not affect the normal operation of the data break facility in the PDP-12. One data break device can be handled without the addition of a multiplexer. The KF 12B has the lowest priority on the bus and break requests from another device are acknowledged during push and restore operations.
The KF 12B control has its own timing generator and is asynchronous with computer timing. A free running 5 mHz oscillator provides the various clocking pulses. An MISS decoder provides the enable levels to enable data on the bus.
5 .2. I Interrupts
Up to 15 levels of interrupts can be accommodated with each level having a two-word vector address. The inter-rupts can be accepted from a prewired option or from up to six external devices. A priority is assigned to each in-terrupt by a jumper module, M905 at location RI 6. Level 0 has the highest priority. Inin-terrupts of a higher priority can occur after executing the first instruction in the interrupt service routine. When the KFI 2B is not enabled (API ON (0)), interrupts are processed through the interrupt cycle in the normal manner. The "TRAP" feature has not been modified by the KFl 2B, but caution should be exercised when using this feature.
5.2.2 Push
When the level of the device requesting an interrupt is greater than the current machine level a Push operation is performed. The Push and Break Req flip-flops are set and the processor enters the Break cycle. The active registers and status levels are stored (pushed) in five consecutive memory locations specified by the contents of the STACK register. (Refer to Table 5-1.) The starting location of the stack is specified by the program (IOT 6776) and is au-tomatically incremented during the push operation. The stack increments and decrements across field boundaries.
The CP is always in 8 MODE at the completion of an interrupt-push operation. If the CP is in LINC mode when a Push occurs it is returned to LINC mode at the completion of a Restore command.
Table 5-1. STACK Register
Location Data Stored
p AC 0-11
P+l PC 0-11
P+2 MODE
o;
FLOW 1; LINK 2; MACHINE LEVEL 8-11P+3 MQ 0-11
P+4 UF 1; IF 2-6; DF 7-11
P =Initial STACK address.
NOTE: the subscript indicates the corresponding memory bits.
5 .2.3 Restore- "POP" (REST-IOT 6771)
Every interrupt subroutine should be terminated with a Restore command. This restores the major registers and machine status from the stack and resumes programming at the memory location specified by the program counter.
For every Push operation performed a Pop (restore) must be performed; however, the two operations do not have to occur in any particular sequence (see Figure 5-13). The Restore command should not be issued when the CP is in a non-interruptable state because an Interrupt Inhibit is set due to the LIP or CIF instruction, or SAVE PC is not set due to a DJR instruction.
CORE { MEMORY
E2
&-i
EB
4. ANOTHER PUSH5.2.4 Vectoring
1. AN EMPTY STACK
EO
/
2. PUSHING A DATUM ONTO THE STACK
E3
E 1
3. PUSHING ANOTHER DATUM
~
ONTO THE STACK
E2
b d ~ ~
EB
E3
b d ~
5. POP 6. PUSH 7, POP
12-0297
Figure 5-13. Illustration of Push and Pop Operations
Each of the 15 interrupt levels has an associated vector address to specify the appropriate interrupt service routine.
The vector address is transferred to the PC during the Push operation, as shown in Figure 5-14. Vector bits 0, 1, and 2 specify the memory field and are set with AC bits 3, 4, and S by an IOT. Vector bits 3 through 9 specify the seven most significant bits of the MA (0-6) and are set with AC bits 0-6 by an IOT. The interrupt level specifies memory address bits 7 through 10 with level "O" setting these bits to zero. A vector address is always an even num-ber address; therefore, each interrupt level is allotted two memory locations.
The following are the vector address assignments, which can reside in any memory field. Vector bits 3 through 9
Figure 5-14. Vector Flow Diagram
Address
The maintenance logic included in the KF 12B provides the capability of checking the major portion of the option for proper operation. Two JOT instructions simulate the 15 interrupt level inputs to check the priority logic and initiate the Push operation.
Instruction IOT 6051 IOT 6052
Function AC0-11 to LEVELS 0-11 ( 1 s transfer)
AC 9, 10, 11 to LEVELS 12, 13, 14 ( 1 s transfer)
The levels remain set for only one computer cycle. This feature allows enough time to initiate a Push function when the selected level has priority and API is enabled.
The KFl 2B features a new two-word instruction called push jump (PUSHJ, IOT 676X). This instruction permits jumping to subroutines across field boundaries in both Linc and PDP-8 Modes. The instruction causes the stacking of the active registers and machine status and automatically jumps to the memory location specified by the 15-bit address associated with the PUSHJ. The instruction code is (IOT) 676X and is similar to an IOT except that X de-fines the new memory field and the following location (P+ 1) specifies the 12-bit memory address of the subroutine.
The PC, which is saved on the stack during the execution of the PUSHJ, points to the location following the two-word instruction as shown in the following example:
Address 15432 15433 15434*
Instruction PUSHJ
1000 CLA
Octal Code 6760 1000 7200 01000 - Programming is transferred to this memory location.
*
Field and PC saved on stack. The program is resumed at this location following a Restore.5. 2 .6 Programming
The following is a typical example of a program to service a Teletype interrupt, which is level 5.
START/CLA
TAD FLDLEV SMLV
CLA
TAD STACK SSTK CLA TAD VEC SVEC APION NOP JMP. -1
*
6412/JMS TTYR* 6413/REST
/set stack and vector fields and machine level /set stack
/set vector /enable KF 12 /wait for interrupt
/go to teletype reader subroutine /restore to status prior to push
*VECTOR ADDRESSES
The REST and PUSHJ commands should not be issued when the processor is in a non-interruptable state due to the following conditions:
a. "Interrupt Inhibit" being set due to the execution of a CIF or LIF instruction;
b. The DJR instruction is being executed or Save PC is not set due to the previous execution of a DJR instruction.
If the REST command is issued and the CP is not in an interruptable condition, the Restore operation will not be performed until the condition becomes satisfactory. If the PUSHJ command is issued and the CP is not in an inter-ruptable condition, the second word of the instruction is treated as a new instruction, and when the condition be-comes satisfactory, the PUSHJ operation will not be properly executed. The ESF Disable Teletype instruction is not effective when the KF 12B is enabled (API ON (1)); the TIY and DP 12 interrupts will always be acknowledged.
When the KF l 2B is not enabled (API ON (0)), the ESF instruction functions in the normal manner. Location zero is not saved on the stack; therefore, caution should be exercised when using this location in conjunction with a LINC JMP instruction.
The next instruction will be executed before an interrupt is processed.
PUSH JUMP to 15 bit address (XXXXX)
Restore machine to previous level
..:-_;,.~~ .. ~:..ti--.
(P+l)
Set current machine level to AC 8-11. If AC7= 1, set stack field to AC0-2 and vector field to AC3-5.
*The KFl 2B must be deselected to execute these instructions (i.e., API ON (0)).
Octal