MEMORY ADDRESSING METHODS

3. 2.1 General

Almost every program, at some time during its execution, will need an item of data stored in memory. Such an operand can be obtained only by specifying the address of the register in which it is stored or to be stored. An instruction which requires a reference to memory can designate the desired location in two ways. It may include the address of the operand as part of the instruction itself and directly address the location of the operand. Or, the instruction may specify the address, not of the operand, but of a register containing the address of the operand, thus indirectly addressing the data storage register.

The need for indirect addressing is readily apparent; with eleven bits required to specify a Data Field address, not much is left of a 12-bit word to use for instruction codes. It is necessary to reduce the number of address bits available within a memory reference instruction, and to use a limited set of directly addressable locations as pointers containing the effective address of the desired data. The LINC instruction set provides for both types of addressing.

3.2.2 Direct Addressing

In LINC programming, direct access to memory registers is limited to the Instruction Field. A full address in this field requires ten bits (0000-1777), leaving only two bits for instruction codes. The three instructions, ADD, STC, and JMP, are described in detail in Paragraph 3.3. The format of a direct-address instruction is shown in Figure 3-2.

Bits 0 and 1 are used for the operation code, bits 2-11 for the address.

OPERATION

CODE ADDRESS

_ _J...___~~~~~~~~~~-A-~~~~~~~~~~

~--y '\

4 5 6 7 8 9 10 11

Figure 3-2. Direct Address Instruction Format 3.2.3 Indirect Addressing: {3-Class

For access to registers in the Data Field, an indirect address is required. The instruction specifies one of a small set of special registers which are used to hold the effective addresses of desired data. The format of these /3-class instructions is shown in Figure 3-3. Bits 3-6 are available for operation codes; bits 8-11, together with bit 7, determine which of four addressing schemes is to be used.

0

~

OPERATION CODE

~~~--A-~~~-,

3 4 5 6 7

. "-y-)

8

Figure 3-3. {3-Class Instruction Format p

9 10 11

3.2.3.1 .(3-Registers - In a .(3-class instruction, the contents of bits 8-11, when not zero, designate one of fifteen registers at locations 0001-0017 of the Instruction Field. The contents of the specified .(3-register are used to determine the effective address of the operand. When the contents of bits 8-11 are zero, the effective address is found in the register which immediately follows the referencing instruction.

Bit 7, the I-Bit, determines the manner in which the register designated by bits 8-11 is to be used in locating the operand. There are four addressing schemes, described in the following table.

Bit 7 (I) Bits 8-11 (.(3)

0 00

00

0 01-17

01-17

Effective Address

The contents of bits 1-11 of the register immediately following the instruction.

The address of the register immediately following the instruction. The operand itself is in this register.

The contents of bits 1-11 of the designated {3-register.

The contents, incremented by 1, of bits 1-11 of the designated 13-register. Ten-bit indexing is used (see text).

In the first scheme, the register which follows the referencing instruction contains the effective address. In the second scheme, the operand itself is in that register. When either of these two schemes is used (that is, when the contents of bits 8-11 are zero), the program counter automatically skips over the register immediately following the instruction, and the next instruction is fetched from the second register following.

The following examples illustrate the use of all four addressing schemes.

The instruction STA (Store Accumulator) causes the contents of the AC to be stored in memory. The operation code for STA is 1040. The register R is the one which immediately follows that containing the STA instruction.

(1) STA 0 Octal code: 1040 I=O, {3=00

Destination of C(AC):

C(R)=2345

Location 2345 (Location 345 in the Data Field)

(2) STA I 0

(3) STA 12

(4) STA I 12

Octal code: 1060 I=l, ,B=OO

Destination of C(AC):

Octal code: 1025 I=O, ,6=12

Destination of C(AC):

Octal code: 1 07 2 I=l, ,B=l 2

Destination of C(AC):

Location R C(OOl 2)=3456

Location 3456 (Location 1456 in the Data Field) C(OOl 2)=3456

Location 3457 (Location 1457 in the Data Field) (The contents of ,B-register 0012 are incremented by 1, and the result, 3457, is used as the effective address.)

In the next example, the use of these addressing schemes in a program sequence is demonstrated. The instruction ADA (Add to Accumulator) adds the operand to the contents of the AC, leaving the result in the AC. The program sequence .~tarting at location l 000 adds the numbers N 1 , N2 , N 3 , and N4 , leaving the sum in the AC.

ADDRESS OCTAL CONTENTS REMARKS

0007 1500 1500 /REPLACED BY 1501 AFTER INDEXING

*1000

1000 1100 ADA /INDIRECT THROUGH 1001, ADD Nl to C(AC)

1001 1477 1477 /ADDRESS OF Nl

1002 1120 ADA /DIRECT TO 1003; ADDS N2 TO C(AC)

1003 3211 N2, 3211

1004 1107 ADA 7 /INDIRECT THROUGH 7 TO 1500, ADDS N3

1005 1127 ADA I 7 /INDIRECT THROUGH 7, INDEXED, ADDS N4

*1477

1477 1234 NI, 1234

1500 1235 N3, 1235

1501 4321 N4, 4321

3.2.3.2 ,B-Register Indexing - When the ,B-indexing scheme is used (I= 1, ,B =I= 00), effective addresses may specify registers in either memory field, but the ,B-register cannot be incremented from one field to the other. Indexing is only over ten bits, as it is in the PC; the two high-order bits are unaffected. Thus, the contents of the ,B-register will be incremented from 1777 to 0000, from 3 777 to 2000, from 5777 to 4000, and from 7777 to 6000. To change access from one field to the other, it is necessary to change the contents of bit 1 of the ,B-register.

Bit 0 of the J3-register has no effect in most indirect references, but it does have a special use in half-word operations, in multipiication, and in character display.

3.2.4 Addressing: a-Class

Three LINC mode instructions - SET, XSK, and DIS - have specialized memory reference schemes. Although each of them accesses memory in a unique way, all make use of one of the registers in locations 0000 through 0017.

These are called a-registers, to differentiate between these instructions and those of the ,8-class.

SET and XSK are described in Section 3.3. DIS is described in Section 3.4.