The MPU, hardware, and firmware initialization process is performed by the PPCBug power-up or system reset. The steps below are a high-level outline; not all of the detailed steps are listed.
1. Set MPU.MSR to known value.
2. Invalidate the MPU’s data/instruction caches.
3. Clear all segment registers of the MPU.
4. Clear all block address translation registers of the MPU.
5. For “dual CPU only” boards (MVME460x or MTX), catch one CPU of a dual CPU and place it in a waiting loop.
6. Initialize the MPU bus to PCI bus bridge device.
7. Initialize the PCI bus to ISA bus bridge device.
8. Calculate the external bus clock speed of the MPU.
9. Delay for 750 milliseconds.
15. Initialize read/write memory controller with the speed of read/write memory.
16. Retrieve the speed of read only memory (Flash).
17. Initialize read only memory controller with the speed of read only memory.
18. Enable the MPU’s instruction cache.
19. Copy the MPU’s exception vector table from $FFF00000 to
$00000000.
20. Initialize the SIO (PC87303/PC87307/PC87308) resources’ base addresses for boards that have the SIO device.
21. Initialize the Z8536 device if the board has the device.
22. Verify MPU type.
23. Enable the super-scalar feature of the MPU (boards with MPC604-type chips only).
24. Initialize the Keyboard Controller (PC87303/PC87307/PC87308) for boards that have the device.
25. Determine the debugger’s Console/Host ports, and initialize the appropriate UART or Graphic devices.
26. Display the debugger’s copyright message.
27. Display any hardware initialization errors that may have occurred.
28. Checksum the debugger object, and display a warning message if the checksum failed to verify.
29. Display the amount of local read/write memory found.
30. Verify the configuration data that is resident in NVRAM, and display a warning message if the verification failed.
31. Calculate and display the MPU clock speed. Verify that the MPU clock speed matches the configuration data, and display a warning message if the verification fails.
Start-up
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32. Display the BUS clock speed. Verify that the BUS clock speed matches the configuration data, and display a warning message if the verification fails.
33. For boards that have a Keyboard Controller display initialization errors that have occurred.
34. Probe PCI bus for supported Network devices.
35. Probe PCI bus for supported Mass Storage devices.
36. Initialize the memory/IO addresses for the supported PCI bus devices.
37. Execute self-test, if configured.
38. Extinguish the board fail LED, if there are no self-test failures or initialization/configuration errors.
39. Execute the configured boot routine, either ROMboot, Autoboot, or Network Autoboot. (PowerPlus architecture boards do not execute a configured boot routine.)
40. Execute the user interface (i.e., the PPCx-Bug> or PPCx-Diag>
prompt).
LED/Serial Startup Diagnostic Codes
These codes are displayed on seven-segment LEDs at key points in the initialization of the hardware devices. Should the debugger fail to come up to a prompt, the last code displayed will indicate how far the initialization sequence had progressed before stalling. The serial port version of the startup codes is enabled by an ENV parameter:
The operating system boot sequence begins at 0x11E0 with the creation of residual data and continues to 0x11EC just before execution is passed to the boot image. The OS may have its own LED codes which are displayed after 0x11EC.
A line feed can be inserted after each serial code is displayed to prevent it from being overwritten by the next code. This is also enabled by an ENV parameter:
Serial Startup Code LF Enable [Y/N]=N?
The following firmware codes are always sent to 7-segment LEDs located at ISA I/O address 0x8C0. These codes can also be sent to the debugger serial port if the ENV parameter “Serial Startup Code Master Enable” is set to ‘Y’. The list of LED/serial codes follows.
Table 1-1. LED/Serial Startup Diagnostic Codes
Code (Hex) Location in Startup
1100 Setting up MSR (startup begins) 1102 Invalidating caches
1104 Determining ROM or RAM execution mode 1106 Setting up machine state register
1108 Setting up CPU’s address translation registers 110A Setting up CPU’s address translation table 110C Shutting down redundant processors 110D Init I/O path out to serial port
110E Initializing super I/O chip (CPU initialization completed) 110F Enable ISA bus access
1110 Initializing raw I/O device 1111 Initialize early stack memory
1112 Getting PHB (PCI Host Bridge) Table Pointer 1113 Disable all caches
1114 Initializing PCI bridge
1116 Initializing the powerup flag indicator 1118 Calculating the speed of the processor bus
Start-up
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111A Waiting for hardware to initialize memory 111C Setting up the DRAM init parameters
111E Initializing DRAM in bridge/memory controller 1120 Setting up debugger memory page area
1122 Calculating and setting DRAM speed 1124 Calculating and setting ROM speed 1126 Enabling instruction cache
1128 Setting up debugger memory page tables
112A Setting up debugger kernel pointers and saving registers 112B Setup the exception control description
112C Setting up buginit section pointers and runtime variables 1130 Retrieving the processor board type
1132 Initializing the Z8536 1134 Initializing local board status 1136 Retrieving the base board type
1138 Checking the level of the ABORT push-button 113A Initializing the interrupt/timer controller 113C Retrieving MPU identifier
113E Enabling super-scalar modes
1140 Adding processor-specific work-arounds 1142 Getting the bus clock speed
1144 Initializing the keyboard controller
Table 1-1. LED/Serial Startup Diagnostic Codes (Continued)
Code (Hex) Location in Startup
114A Initializing RAVEN PCI space
114C Initializing RAVEN time base registers 114D Initialize RAVEN interrupt controller 114E Initializing FALCON ROM
1150 Initializing VME bridge 1152 Initializing ISA bridge 1154 Sending speaker beep 1160 Checking abort switch state 1162 Initializing exception handling 1164 Initializing board identifier structure 1166 Initializing point break table 1168 Initializing macro subsystem 116A Initializing configuration data area 116C Initializing board information data area 116E Initializing I/O (character) subsystem 1170 Initializing register file
1172 Getting bridge pointer
1174 Setting up local memory pointers 1176 Setting up local memory size variables 1178 Displaying sign-on messages
117A displaying board initialization errors 117C Verifying the ROM checksum
117E Displaying memory size and misc errors 1180 Displaying MPU clock speed
1182 Verifying MPU clock speed 1184 Displaying bus clock speed 1186 Initializing network I/O subsystem
Table 1-1. LED/Serial Startup Diagnostic Codes (Continued)
Code (Hex) Location in Startup
Start-up
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1188 Initializing disk I/O subsystem 118A Initializing direction flags
118C Initializing NVRAM (PReP) environment 118E Initializing residual data pointer
1190 Initializing input/output pointers 1192 Initializing diagnostic subsystem
1194 Setting up special init section pointers and runtime variables 1196 Initializing abort switch
1198 Setting up board suffix and return environment 11A0 Retrieving the processor board type
11A2 Displaying memory warning and MPU configuration 11A4 Clearing MPU idle semaphores
11A6 Waiting for MPU logins
11A8 Displaying MPU status information 11AA Setting up DRAM and bridge pointers 11AC Initializing DRAM ECC/parity 11AE Displaying DRAM information 11B0 Setting up misc. L2 cache variables 11B2 Setting up L2 cache size variables
11B4 Initializing and flushing L2 cache data parity 11B6 Displaying L2 cache parity state
11B8 Reading NVRAM contents
Table 1-1. LED/Serial Startup Diagnostic Codes (Continued)
Code (Hex) Location in Startup