The DLVll-E or DLVll-F module can be installed in any slots in the LSI-ll backplane, except the first four slots (the LSI-ll processor always occupies the first slots). Do not leave any unused option locations between the processor and the DLVll-E or DLV11-F. An open slot would break the inter-rupt acknowledge daisy chain. The priority of the module is determined by its proximity to the proces-sor on the bus (refer to Figure 3-5). The closer the slot is to the procesproces-sor module, the higher the interface module's priority.
Determine the appropriate slot for the module. For example, if a DLVll-E is interfacing commu-nications lines from a host computer, it would normally be placed in the slot closest to the processor module, followed by the module interfacing the console terminal. Refer to Microcomputer Handbook (DIGITAL part number EB 06583 76) for system considerations.
S1
-Foll-FR
C1
-
M1ifni! l~ '---___ ---'
II
I" IIIII
y--B H
Figure 3-1 DLV11-E Jumper Locations
----
PB11-5172
[" ~ liiiilili
II II IIIII Q
C29;a~ ilI~ M~!!:~
M"ItIIHC"",,CO
»»»
III111
Qp"NM
a: a: a: a:
IIII
11-5173
Jumper A3-AI2
V3-V8
RO-R3
TO-T3
BG P E
I, 2
PB
C,CI
S, SI
H
Table 3-1 Jumper Definitions NOTE
This table pertains to both the DLVll-E and the DLVll-F, except as noted. Jumpers are inserted to enable the function they control except for those jumpers that indicate negation (such as "-B" and
"B"). Negated jumpers are removed to enable the functions they control.
Function
These jumpers correspond to bits 3-12 of the address word. When inserted, they will cause the bus interface to check for a True condition on the corresponding address bit.
Used to generate the vector during an interrupt transaction. Each inserted jumper will assert the corresponding vector address bit on the LSI-II bus.
Receiver and transmitter baud rate select jumpers, during common speed operation.
Receiver only baud rate select jumpers during split speed operation (see Table 3-2).
Transmitter baud rate select jumpers during split speed operation.
Both receiver and transmitter baud rate if maintenance mode is entered during split speed operation (see Tale 3-2).
Jumper is inserted to enable Break generation.
Jumper is inserted for operation with parity.
Removed for even parity; inserted for odd parity. Receiver checks for appropriate parity and transmitter inserts appropriate parity.
These jumpers select the desired number of data bits (see Table 3-3).
Jumper is inserted to enable the programmable baud rate capability.
These jumpers are inserted for common speed operation. (Note that S and Sl must be removed when C and Cl are inserted.)
Inserted for split speed operation. (Note that C and Cl must be re-moved when Sand SI are inserted.)
This jumper is inserted to assert BHAL T L when a framing error is received, except when the Maintenance bit is set. This places the LSI-II in the halt mode.
Jumper
Table 3-1 Jumper Definitions (Cont) Function
Jumper B is inserted to negate BDCOK H when a BREAK signal or framing error is received, except when the Maintenance bit is set. This causes the LSI-II to reload the bootstrap. (Jumper -B orB must be removed when B is inserted.)
Jumper is removed to force DATA TERMINAL READY signal on.
Jumper is removed to force REQUEST TO SEND signal on.
This jumper is inserted to enable normal transmission of the REQUEST TO SEND signal.
Inserted to enable transmission of the FORCE BUSY signal (for Bell model 103E data sets).
These three jumpers are inserted to make the 20 rnA current loop receiver active. (Jumpers IP and 2P must be removed when lA, 2A, and 3A are inserted.)
These jumpers are inserted to make the 20 rnA current loop receiver passive. (Jumpers lA, 2A, and 3A must be removed when I P and 2P are install ed. )
Inserted to make the 20 rnA current loop transmitter active. (Jumpers 3P and 4P must be removed when 4A and 5A are inserted.)
Inserted to make the 20 rnA current loop transmitter passive. (Jumpers 4A and 5A must be removed when 3P and 4P are inserted.)
Jumper is removed to enable the error flags to be read in the high byte of the Receiver Buffer.
When inserted, enables maintenance bit.
Table 3-2 Baud Rate Selections
Bit Bit Bit Bit Bit
Program Control 15 14 13 12 11*
Receive Jumpers R3 R2 Rl RO Baud
Transmit Jumpers T3 T2 Tl TO Rate
I I I I 50
I I I R 75
I I R I 110
I I R R 134.5
I R I I 150
I R I R 300
I R R I 600
I R R R 1200
R I I I 1800
R I I R 2000
R I R I 2400
R I R R 3600
R R I I 4800
R R I R 7200
R R R I 9600
I
=
Jumper Inserted=
Program Bit Cleared.R
=
Jumper Removed=
Program Bit Set.*Bit 11 of the XCSR (Write Only Bit) must be set in order to select a new baud rate under program control. Also, jumper PB must be inserted to enable baud rate selection under program control.
Table 3-3 Data Bit Selections Jumpers
2 1
I I
I R
R I
R R
Number of Data Bits 5
6 7 8
Table 3-4 Jumper Configuration When Shipped
Jumper Jumper State
Designation DLVII-E DLVll-F Function Implemented
A3 R I Jumpers A3 through Al2 implement device address
A4 I R 1756lX for the DLVII-E and 17756X for the DLVII-F.
A5 I R The least significant octal digit is hardwired on the module A6 I R to address the four device registers as follows:
A7 R I
A8 R R X=O RCSR
A9 R R X=2 RBUF
AIO I R X=4 XCSR
All R R X=6 XBUF
Al2 R R
V3 I I This jumper selection implements interrupt vector address V4 I R 300s for receiver interrupts and 304s for transmitter V5 I R interrupts on the DLVII-E. On the DLVll-F it selects V6 R I 60s for receiver interrupts and 64 s for transmitter
V7 R I interrupts.
V8 I I
RO I I The module is configured to receive at 110 baud.
RI R R
R2 I I
R3 I I
TO I I The transmitter is configured for 9600 baud if split speed
T1 R R operation is used.
T2 R R
T3 R R
BG \ I I Break generation is enabled.
P R R Parity bit is disabled.
E R R Parity type is not applicable when P is removed.
1 R R Operation with 8 data bits per character.
2 R R
PB R R Programmable baud rate Junction disabled.
Table 3-4 Jumper Configuration WhenShipped (Cont)
Jumper Jumper State
Designation DLVll-E ; DLVII-F Function Implemented
S R R Split speed operation disabled.
Sl R R
H R I Halt on framing error disabled on DLVII-E;enabled
on DLVll-F.
B R R Boot on framing error disabled.
-B I N/A
13
N/A I-FD I N/A The DATA TERMINAL READY signal is not forced
continuously True.
-FR I N/A The REQUEST TO SEND signal is not forced continuously True.
RS I N/A The circuitry controlling the REQUEST TO SEND signal is enabled.
FB R N/A The FORCE BUSY signal is disabled.
lA N/A I The 20 rnA current loop receiver is configured as an
2A N/A I active receiver.
3A N/A I
lP N/A R
2P N/A R
4A N/A I The 20 rnA current loop transmitter is configured for
5A N/A I active operation.
3P N/A R
4P N/A R
-
EF N/A I Error flags are enabled on DLVI1-E; disabled on DLVII-F.M R R Factory test jumpers. Not defined for field use.
Ml R R
MT N/A R Maintenance bit disabled.
Module/Mode DLVII-E Modem Control
DLVII-F
Table 3-5 Module Application Examples Equipment Supported Bell Data Sets, Models:
103 202C 202D 212A
Bell Model 103 Data Set (in automode).
Teletype Model 37 Teletypewriter EIA Data Leads Only
DLVII-F
Teletype Model 33 and 35 Teletypewriters DIGITAL equipment:
20 rnA Current Loop LA36 DECwriter (read/write) LA35 DECwriter (read only)
OLV11-E
40 PIN
VT05B Alphanumeric Terminal VT50 DECscope (l2Iine) VT52 DECscope (24 line) RT02 Alphanumeric Terminals DFOI-A Acoustic Telephone Coupler LT33 Teletypewriter
LT35 Teletypewriter
DATA SET CONTROL
CONN OB-25
~~
________________ B_CO_5_C __________________[j
Figure 3-3 DLVII-E Cabling Example
DATASET BELL 103 BELL 202
11- 4961
DLVII -F
DLV"-F ( RECEIVER PASS IVE, TRANSMITTER
ACTIVEl
DLV11-F ( RECEIVER PASSIVE, TRANSMITTER
PASSIVEl
DLV11 -F
DLV"-F
CURRENT LOOP MODE
40 PIN
MATE-N-CONN. LOK
r:l
BC05Mr:l
LJI---1LJ
M L t - - - i40 PIN MATE-N- MATE-N- 40 PIN
CONN. LOK LOK CONN.
tJ
BC05M00
BC05FGtJ
BC05Mtl
40 PIN MATE-N- MATE-N- 40 PIN
CONN. LOK LOK CONN.
tJt--_B_C_0_5M _ _ 8 GI--_BC_0_5_F---IG 8 t - -_ _ B_C_0_5_M ____ t J
ErA" DATA LEADS ONLY" MODE 40 PIN
CONN DB-25 DB-25
[:]~
_ _ _ B_C_0_5C _ _ _~[:]
BC03PNULL MODEM CABLE
40 PIN
CONN DB -25
[:]~ _ _ _ _ _ _ _ _ _ _ B_C_0_5_C _ _ _ _ _ _ _ _ _ _ _ [ : ]
Figure 3-4 DLVII-F Cabling Examples
LA36 VT52 TTY
DLV11-F ( RECEIVER PASSIVE, TRANSMITTER
ACTIVE)
DLII-C
EIA/CCITT TERMINAL
VT06
MODEL 103 DATASET (AUTO MODEl
, , - 4962
CONNECTOR BLOCK
VI EW FROM MODULE SIDE OF BACKPLANE
A B C o
KDll-F
MSVl1 - B DLVl1- E MSVl1- B RXVl1
REVl1 DRVl1
Figure 3-5 Typical Backplane Configuration
2