The 4-bit transceiver is a 20 pin DIP, low-power Schottky device for primary use in peripheral device interfaces, functioning as a bidirectional buffer between a data bus and peripheral device logic. In addition to the isolation function, the device also provides a comparison circuit for address selection and a constant generator, useful for interrupt vector addresses. The bus I/O port provides high-imped-ance inputs and high-drive (70 rnA) open-collector outputs to allow direct connection to a computer's data bus structure. On the peripheral device side, a bidirectional port is also provided, with standard TTL inputs and 20 rnA tristate drivers. Data on this port is the logical inversion of the data on the bus side.
Three address jumper inputs are used to compare against three bus inputs and to generate the signal MATCH. The MATCH output is open-collector, which allows the output of several transceiver's to be
Three vector jumper inputs are used to generate a constant that can be passed to the computer bus.
The three inputs directly drive three of the bus lines, overriding the action of the control lines.
Two control signals are decoded to give three operational states: receive data, transmit data, and disable.
Maximum current required from the Vee supply is 100 rnA.
Figure A-7 is a simplified logic diagram of the DC005 IC. Timing for the various functions is shown in Figure A-8. Signal and pin definitions for the DC005 are presented in Table A-4.
+VCC-@
+VCC 16 ENAST H
ROSTA H
SET 0 I
ENAOATA H 0
VECTOR H VCC
VECROSTB H ROSTA H
C 0 0 BOIN L ENAST H
ENACLK H 14 C CLR 0 CLR INITO L ENAOATA H
BINIT L ENACLK H
BIAKO L ENBCLK H
C CLR BIAKI L ENBOATAH
BIRO L ENBST H
GNO ROSTB H
BIAKI L 07
BINIT L BIAKO L
BOIN L BIRO L
ENBST H VECTOR H
:> 0
I
W
ENBCLK H 13 0
CLR 0
+VCC C 0
ROSTB H 10 CLR IK
~GNO INITO L
IC - 0173
BINIT L
I
~?? 1300 :~MINI
I I
1 I
~
7-35 --~I---INITO L -+t I, I
ENA DATA H
ENA CLK H
ENA ST H
ROSTA H
BIRO L
BDIN L
BIAKI L
VECTOR H
BIAKO L
NOTE:
I I
,
1,
30 MIN~ ~~ ____________________________ -Jr---l~
________________________ ___
I I
7-30~ F
15-65-':
, b
L.. ____-'--;:,...F
20 - 9035 MIN--:
t:-
...., - _
... ,1 1
, 1
10-45-:
F-i r-
10 - 4535 MIN--1
,
12-55--1
, , , ,
r-~ F
12-55Times are in nanoseconds
11-4150
Figure A-2 De003 "A" Interrupt Section Timing Diagram
BIN IT L
Pin
Table A-I DCOO3 Pin/Signal Descriptions Description
INTERRUPT VECTOR GATING signal. This signal should be used to gate the appropriate vector address onto the bus and to form the bus signal called BRPL Y L.
VECTOR REQUEST "B" signal. When asserted, indicates RQST "B" service vector address is required. When unasserted, indicates RQST "A" service vector address is required. VEC-TOR H is the gating signal for the entire vector address. VEC RQST B H is normally bit 2 of the vector address.
BUS DATA IN. This signal, generated by the processor BDIN, always precedes a BIAK signal.
INITIALIZE OUT signal. This is the buffered BINIT L signal used in the device interface for general initialization.
BUS INITIALIZE signal. When asserted, this signal brings all driven lines to their unasserted state (except INITO L).
BUS INTERRUPT ACKNOWLEDGE signal (OUT). This signal is the daisy-chained signal that is passed by all devices not requesting interrupt service (see BIAKI L). Once passed by a device, it must remain passed until a new BIAKI L is generated.
BUS INTERRUPT ACKNOWLEDGE signal (IN). This sig-nal is the processor's response to BIRQ L true. This sigsig-nal is daisy-chained such that the first requesting device blocks the signal propagation while nonrequesting devices pass the signal on as BIAKO L to the next device in the chain. The leading edge of BIAKI L causes BIRQ L to be unasserted by the requesting device.
ASYNCHRONOUS BUS INTERRUPT REQUEST from a device needing interrupt service. The request is generated by a true RQST signal along with the associated true interrupt enable signal. The request is removed after the acceptance of the BDIN L signal and on the leading edge of the BIAKI L signal, or the removal of the associated interrupt enable, or due to the removal of the associated request signal.
DEVICE INTERRUPT REQUEST SIGNAL. When asserted, with the enable "A" flip-flop asserted, will cause the assertion of BIRQ L on the bus. This signal line normally remains asserted until the request is serviced.
Pin 11 16
12 15
13 14
Table A-I DC003 Pin/Signal Descriptions (Cont) Signal
ENBSTH ENASTH
ENBDATAH ENADATAH
ENBCLKH ENACLKH
Description
INTERRUPT ENABLE "A" STATUS signal. This signal indicates the state of the interrupt enable "A" internal flip-flop, which is controlled by the signal line ENA DATA H and the ENA CLK H clock line.
INTERRUPT ENABLE "A" DATA signal. The level on this line, in conjunction with the ENA CLK H signal, determines the state of the internal interrupt enable "A" flip-flop. The out-put of this flip-flop is monitored by the ENA ST H signal.
INTERRUPT ENABLE "A" CLOCK. When asserted (on the positive edge), interrupt enable "A" flip-flop assumes the state of the ENA DATA H signal line.
ENB H BSYNC L
VECTOR H VCC
BDAL2 L ENB H
BDALI L RXCXH
BDALO L SEL6 L
BWTBT L SEL4 L
BSYNC L SEL2 L
BDIN L SELO L
BRPLY L OUTHB L
BDOUT L OUTLB L
GND INWD L
...-vvv-
+VCCI--~---~D I~---_.---, LATCH ENS
X~-.---IG 0 BDAL2 L 21---I-~
G O~ ______ -+ ________________________ ~D~A~L~2
BDAL 1 L 031---I-~D 1 Ot
LATCH DAL 1
G
O~---~---~~~BDOUT L
BDIN L
DECODER
~ VCC
§-- GND
10---417 SEL 6 L b---I16 SEL 4 L
1O----~15 SEL 2 L 10----114 SEL 0 L
OUTHB OUTLB
RXCX H
BRPLY VECTOR INWD L Ie-01
Figure A-4 DC004 Simplified Logic Diagrar
Table A-2 DC004 Signal Timing vs Output Loading
With Output Output
Respect Test Being Being Figure A-S
Signal to Signal Condo Asserted Asserted Ref.
Min Max Min Max
(ns) (ns)
Se1 (0,2,4,6) L BSYNC L Load B 15 35 5 25
t5' t6
Load C 15 40 5 30
OUTLB L BDOUT L Load B 5 25 5 25
Load C 5 30 5 30 t9' tlO
OUTHB L DBOUT L Load B 5 25 5 25
LoadC 5 30 5 30 t9' tlO
INWDL BDIN L Load A 5 25 5 25
Load B 5 30 5 30 t11,t12
Pin 18 BRPLY L OUTLB L 20 60 -10 45
Connection (Load A) (Load B) t13' t14
RX= IK ±5%
350n ±5% BRPLY L OUTHB L 20 60 -10 45
15 pf±5% (Load A) (Load B) t13' tl4
BRPLY L INWDL 20 60 -10 45
t13' t14 (Load A) (Load B)
BRPLY L VECTORH 30 70 0 45
t13' t14 (Load A)
Pin 18 BRPLY L OUTLB L 300 400 -10 45
t13' t14
Connection (Load A) (Load B)
RX = 4.64K ±1%
BRPLY L OUTHBL 300 400 -10 45
t13' t14 (Load A) (Load B)
CX=220pf±l% BRPLY L INWDL 300 400 -10 45
(Load A) (Load B) t13' t14
BRPLY L VECTORH 330 430 0 45
t13' t14 (Load A)
BDAL (2,l,O)L
~25 MINI25MIN~
ENB
H~J~N ~~N~
BSYNC L
I I
SEL (0,2,4,6) L
~T6F
NOTE:
BWBTL~
1 1 1
BDOUT L 15 MIN.--l
I
1
~
1
I
~-_____
15 MIN.-:!.. ~~.---*----~-L-I I+-I __
1 1
I 1
OUTHB L _ _ _ _ _ _ _ _ _ _ _ _ --i1i--, I
OUTLB L
--l
T9t= -\
noF
BDIN L
---'Tll~
1001 .. - - - * - - - - -... 1 ... ___-I I
IWD L - - \ T 1 2 F
1 1
I 1
1 I
--l
T13~L-
_ _ _ _ --'_.;..!_I._1~~ (=
2.4 VBRPLY L
I I
I 1
VECTOR H
I 11+- .. --*---+1-1
I I
Rx Cx H
4
T15F ---1
n6L~
_ _ _ _ _ _ _ _ _ _ _ _ _*
TIME REQUIRED TO DISCHARGE Rx Cx FROM ANY CONDITION ASSERTED = 150nsTimes are In nanoseconds
11- 4348
Figure A-5 DC004 Timing Diagram
FROM OUTPUT
Pin
2 3 4
5
6
7
Vee Vee Vee
60n 280n
FROM FROM ) 0
OUTPUT OUTPUT
I 150,F
rOO'F roc
DIODE -FD777-=
LOAD A LOAD B LOAD C
11-4349
Figure A-6 DC004 Loading Configuration for Table A-2
Signal VECTORH
BDAL2 L BDALl L BDALOL
BWTBTL
BSYNCL
BDINL
Table A-3 DC004 Pin/Signal Descriptions Description
VECTOR. This input causes BRPL Y L to be generated through the delay circuit. Independent of BSYNC Land ENB H.
BUS DATA ADDRESS LINES. These signals are latched at the assert edge of BSYNC L. Lines 2 and I are decoded for the select outputs; line 0 is used for byte selection.
BUS WRITE/BYTE. While the BDOUT L input is asserted, this signal indicates a byte or word operation: Asserted
=
byte, unasserted=
word. Decoded with BOUT L and latched BDALO L to form OUTLB Land OUTHB L.BUS SYNCHRONIZE. At the assert edge of this signal, address information is trapped in four latches. While unas-serted, disables all outputs except the vector term of BRPL Y L.
BUS DATA IN. This is a strobing signal to effect a data input transaction. Generates BRPL Y L through the delay circuit and INWD L.
Pin
Table A-3 DC004 Pin/Signal Descriptions (Cont) Description form OUTLB Land OUTHB L. Generates BRPLY L through the delay circuit.
IN WORD. Used to gate (read) data from a selected register on to the data bus. Enabled by BSYNC L and strobed by BDIN L.
OUT LOW BYTE, OUT HIGH BYTE. Used to load (write) data into the lower, higher, or both bytes of a selected register.
Enabled by BSYNC L and decode of BWTBT L and latched BDALO L, and strobed by BDOUT L.
SELECT LINES. One of these four signals is true as a function of BDAL2 Land BDALl L if ENB H is asserted at the assert edge of BSYNC L. They indicate that a word register has been selected for a data transaction. These signals never become asserted except at the assertion of BSYNC L (then only if ENB H is asserted at that time) and, once asserted, are not un asserted until BSYNC L becomes unasserted.
EXTERNAL RESISTOR CAPACITOR NODE. This node is provided to vary the delay between the BDIN L, BDOUT L, and VECTOR H inputs and BRPL Y L output. The external resistor should be tied to VCC and the capacitor to ground. As an output, it is the logical inversion of BRPL Y L.
ENABLE. This signal is latched at the asserted edge of BSYNC L and is used to enable the select outputs and the address term ofBRPLY L.
JAI L VCC
JA2 L JA3 L
MATCH H DATO H
REC H DATI H
XMIT H JV3 H
DAn H JV2 H
DAT2 H JVI H
BUS3 L MENB L
BUS2 L BUSO L
GND BUSI L
JA3 L
~--+---~----,03 MATCH H MENB L
8-TRANSMIT DATA TO BUS
XMIT H
REC H (GROUND)
r-
5 TO 30n.r-
5 TO 30n.---BUS L - OUTPUT
1 1 1
5 TO 25no-l I-
-I
1-5 TO 25noOAT H - INPUT - - - . - - - ;
1 ___ ---IIr----'---r----
..RECEIVE DATA FROM BUS <BUS INITIALLY HIGH)
XMIT H (GROUND)
OAT H - OUTPUT
REC H _ _ _ _ _ _
J-I I
::j
r-
0 TO 30no -I I-0 TO 30no--~---~J!I ---~~
-I
I-BT030n.BUS L-INPUT
---,...---11'--___________ '--__
RECEIVE DATA FROM BUS <BUS INITIALLY LOW)
XMIT H (GROUND)
I I
-l
I+-
0 TO 30n.-l
i-OTO 30n.--.J I
-l
I-B TO 30noI
REC H
---1
OAT H - OUTPUT
BUS L-INPUT
VECTOR TRANSFER TO BUS
I I
-l I - 20no MAX
-l
I - 20no MAXI I
JV H
BUS L - OUTPUT
ADDRESS DECODING
BUS L - INPUT
X
-1
j+-to TO 40noI X ~
to TO 40no-l 1-5 TO 40no
-I
MATCH H
__________
~--~---JMENB L
I I
RECEIVE MODE LOGIC DELAY
XMIT H
REC H
I-40 TO 90no
DAT(3:0) H (OUTPUT) _ _ _ _ _ _ _ _ _ _ _
..JI'--_____________ _
fI-4892
Pin
Table A-4 DC005 Pin/Signal Descriptions Function
BUS DATA. This set of four lines constitutes the bus side of the transceiver. Open-collector outputs; high-impedance inputs.
LOW
=
1.PERIPHERAL DEVICE DATA. These four tri-state lines car-ry the inverted received data from BUS (3:0) when the trans-ceiver is in the receive mode. When in transmit data mode, the data carried on these lines is passed inverted to BUS (3:0).
When in the disabled mode, these lines go open (hi-z).
HIGH
=
1.VECTOR JUMPERS. These inputs, with internal pull-down resistors, directly drive BUS (3: 1). A low or open on the jumper pin will cause an open condition on the corresponding BUS pin if XMIT H is low. A high will cause a one (low) to be trans-mitted on the BUS pin. Note that BUSO L is not controlled by any jumper input.
MATCH ENABLE. A low on this line will enable the MATCH output. A high will force MATCH low, overriding the match circuit.
ADDRESS MATCH. When BUS (3:1) match with the state of J A (3: 1) and MENB L is low, this output is open; otherwise, it is low.
ADDRESS JUMPERS. A strap to ground on these inputs will allow a match to occur with a one (low) on the corresponding BUS line; an open will allow a match with a zero (high); a strap to Vee will disconnect the corresponding address bit from the comparison.
CONTROL INPUTS. These lines control the operational of the transceiver as follows:
REC XMIT
DISABLE: BUS, DAT open XMIT DATA; DAT Bus RECEIVE: BUS DAT RECEIVE: BUS DAT
To avoid tristate overlap conditions, an internal circuit delays