Max Units

. --_._.

_ ^{.. ..,.., ...}

-SWITCHING CHARACTERISTICS

(TA = O°C to 70°C; Vp = 5V ± 10%)

Parameter Symbol Min Typ

Tone Time: for detect ton 40

-, for reject ton

-

-Pause Time: for detect toft 40

-for reject toft

-

-Detect Time td 25

-Release Time tr 25

-Data Setup Time tsu

7

-Data Hold Time th

7

9

DV Clear Time tel

-

¹⁶⁰

CLRDV Pulse Width tpw 200

-ED Detect Time ted 5

-ED Release Time ter 0.5

-Output Enable Time (Note 11)

ten

-

200

C L

=

^{50 pF, R L}

=

^{1 kohm}

Output Disable Time (Note 11)

tdis 150

CL

=

35 pF, R L

=

500 ohms

-Output Rise Time (Note 11)

t rise 200

CL

=

^{50 pF}

-Output Fall Time (Note 11)

t'all 160

CL

=

^{50 pF}

-Note: 11. RL and CL are parallel impedances.

4·6

CS202/3

Max Units

-

^ms

20 ms

-

^ms

20 ms

46 ms

50 ms

-

^us

10 us

250 ns

-

^ns

22 ms

18 ms

300 ns

200 ns

300 ns

250 ns

DS6F1

..,-•• ..,..,I11III •

. --- ._.

_ ^{.. ..,_ ...}

-Any Oigital Output

EN

CS202/3

trise tfall

___ A

^70%

\3"",OO.:.::YO~

^{_ _}

l

^{10-ten Ft diS---<}

Hi-Z 70% Vall'd Data 70% Hi-Z

01, 02, 04, 08 - - - {

>--""'3:..::.0⁰:..::.Yo _ _ _ _ =30::...:O/c""'o

ANALOG IN

01,02,04,08

OV

CLROV

DS6F1

/--ton

+

-1

Tone Burst 1

I

H1t

^d

^I

I I

^Data

toll-1

pause

11---

Tone Burst 2

Data H t su rt rf-th-1

I I I I

~tcl1

I L

Figure 1 . Timing Diagram

II

4·7

.. - ... .

. --- ._.

_ ^....

^{. "}

^...

-GENERAL DESCRIPTION

The CS202 and CS203 are complete Dual Tone MuItifrequency (DTMF) Receivers designed to detect 12 or 16 digits in either a 2-of-7 or 2-of-8 tone selection scheme. These devices provide all of the necessary filtering and require only an ex-ternal 3.5795 MHz colorburst crystal and a resis-tor to provide a reference clock. Both devices are designed using a high-density, low-power CMOS technology, and provide the best perfor-mance at the lowest cost.

The CS202 and CS203 have filtering on board to guarantee the best signal-to-noise performance possible. The DTMF signal is passed through a dial tone reject filter to reduce dial tone inter-ference, and is then separated into low and high groups using two bandsplit filters. The output of each bandsplit filter contains frequency com-ponents from only one DTMF tone group.

Table 1 - DTMF Dialing Matrix

High-Band group must simultaneously contain only one valid DTMF tone. Detection of the two tones is accomplished with a digital algorithm. The sinusoidal filter output waveforms pass through a pair of hard limiters. The decoder takes the resultant square waves and measures their periods. This period measurement varies with jit-ter created by any extraneous signals within the signal passed to the limiter. The period measure-ment is averaged over a number of cycles and compared to a range of period measurements

CS202/3

representing the three or four expected tones. If both bands have a valid tone decoded, the ED signal (CS203 only) will go high.

After two valid tones have been recognized by the decoder, the tones are subjected to a detect timing cycle. The two tones must remain valid for 20 to 40 ms for DV to go high, indicating that a valid digit has been decoded. This prevents voices or other in-band noise from creating a false trigger.

After a valid digit is indicated, the timing circuit will then enable a timing chain that detects drop-outs. If a signal drop of less than 20 ms duration occurs, it will be ignored. This timing prevents false triggering due to keybounce or other signal interruptions. Any drop-out in excess of 40 ms is considered a valid release; the receiver is reset (DV goes low), and all decoded outputs are cleared for the next decode.

Interfacing to the CS202 and CS203

The CS202 and CS203 have analog, data and control interfaces. The analog interface deter-mines how an analog voice channel is connected.

The data interface controls the method of ex-tracting output data. The control interface deter-mines what signals are detected and how they are presented to the data interface.

The analog interface consists of only one signal:

ANALOG IN. The ANALOG IN signal can be either DC-coupled or AC-coupled using a 0.01J,LF capacitor. Care must be taken not to ex-ceed the voltage requirements of the pin. It is also desirable to add a simple RC lowpass filter to bandlimit the input to the voice band (100 Hz to 3.4 kHz) so that high frequency noise near the 55.9 kHz internal sampling frequency is not aliased into the voice band by the internal switched-capacitor filters.

DS6F1

.. - ^... _.

strobed (synchronous) or handshake output. In the strobe mode, CLRDV is held low and DV is used as a data clock to strobe valid information from the data pins (Dl, D2, D4, D8). The hand-shake mode is useful in an edge-triggered en-vironment. The DV pin is used to generate an in-terrupt which forces the system to read informa-tion from the data pins. The interrupt (DV), is then cleared by taking CLRDV high momentari-ly. When there is a need to interface the receivers to a bus, the CS202 and CS203 can be three-state controlled by the EN pin. The EN pin must be held high to take the devices out of the high im-pedance state and into a data output mode. Con-versely, taking EN low will force the devices into high impedance states and prevent bus conflicts.

Table 2 - Digital Encoding ofDTMF Signal Hexadecimal Binary 2-of-8 Oigit

When this pin is low, all tones are decoded.

Clock Generation

The CS202 and CS203 provide two separate means of clock generation, internal and external.

With internal clock generation, a 3.5795 MHz crystal is tied between XIN and XOUT, a IMn resistor is tied in parallel with the crystal to guarantee oscillation, and the XEN signal is tied high enabling the crystal oscillator. In this mode, the ATB pin is a 447.443 kHz clock output which can be used to drive up to 10 other CS202 and CS203 devices that are in the external clock mode.

Figure 3 - Clock Options

The external clock mode is obtained by tying

.. - ...

^~.

.. - .. -._.

_ ^{.... - ...}

-Power Supply

The CS202 and CS203 operate on a 5V

±

10%

power supply. As with any circuit that combines analog and digital signals, good power supply decoupling is recommended. For best perfor-mance, a 0.1j.iF non-polarized (mylar, ceramic, etc.) capacitor should be tied between Vp and GND. Additional low frequency protection can be achieved with a 10j.iF electrolytic capacitor connected in parallel with the 0.1j.iF capacitor.

The decoupling capacitors should be situated as close to the device as possible.

DATA OUTPUT 1 01 HEX/BINARY 2-0F-8 SELECT HEXlB28

DATA ENABLE EN

1633Hz INHIBIT IN1633

POWER vp

NO CONNECT N/C

GROUND GND

OSCILLATOR ENABLE XEN DTMF INPUT ANALOG IN 9

ATB ALTERNATE TIME BASE XIN CRYSTAL INPUT XOUT CRYSTAL OUTPUT GND GROUND

02 DATA OUTPUT 2 04 DATA OUTPUT 4 08 DATA OUTPUT 8 elROV DATA VALID CLEAR ov DATA VALID

ATB ALTERNATE TIME BASE XIN CRYSTAL INPUT XOUT CRYSTAL OUTPUT GNO GROUND

DS6F1

--- ^---

---

^CS202/3

PIN DESCRIPTIONS

Power Supplies

Vp - Positive Power Supply, PIN 5.

Nominally, +5 volts.

GND - Ground, PINS 7 and 10.

Negative power supply pins. Normally connected to system ground (0 volts). Pin 10 must be connected to ground. Pins 7 and 10 are connected together internally so that an external connec-tion of pin 7 to ground is opconnec-tional. If pins 7 and 10 are both connected to ground, they should be tied to the same ground trace on the PCB.

Oscillator

XIN - Crystal Input, PIN 12.

Input pin for the crystal oscillator. One lead of the crystal and its bias resistor are tied to this pin.

XOUT - Crystal Output, PIN 11.

Crystal oscillator output pin. One lead of the bias resistor and crystal are tied to this pin.

XEN - Oscillator Enable, PIN 8.

Setting XEN to logic 1 puts the device in the internal clock mode. The on chip oscillator is used as the clock and the ATB pin is configured to output 447.443 kHz (fosd8). Setting XEN to logic 0 puts the device in the external clock mode. In the external clock mode, a clock signal input to the ATB pin is used to clock the device; the internal oscillator is not used.

ATB - Alternate Time Base, PIN 13.

Inputs

In the internal clock mode (XEN

=

1), ATB will output a 447.443 kHz clock (fose/8). In the ex-ternal clock mode (XEN = 0), a 447.443 kHz clock should be input to the ATB pin.

ANALOG IN - DTMF Input, PIN 9.

Signal channel input. The DTMF tones to be decoded are input into this pin.

DS6F1 4-11

a

~

....

^~~~.

. --- ^._.

- ..

^~-

...

-IN1633 - 1633 Hz Inhibit, PIN 4.

CS202/3

Setting IN1633 to logic 1 causes the device to not decode tone pairs which contain 1633 Hz tones. IfIN1633 is set to logic 0, the device will decode all 16 DTMF tone pairs.

HE:xiB28 - HexlB28, Binary 2-of-S Select, PIN 2.

Setting HEXIB28 to logic 1 causes the code corresponding to the decoded DTMF signal to be output in a Hexadecimal format. Data will be output in a Binary 2 of 8 format if HEXIB28 is set to logic O.

EN - Data Enable, PIN 3.

Holding EN at logic 1 enables the data outputs. Setting EN to logic 0 causes the data outputs to go to a high impedance state.

CLRDV - Data Valid Clear, PIN 15.

Setting CLRDV to a logic 1 clears a data valid indication on DV.

Outputs

Dl; D2; D4; DS - Data Outputs, PINS 1; IS; 17; 16.

A code corresponding to a decoded DTMF signal is output on these pins. This output can be in hexadecimal (HEX!B28

=

1) or binary 2 of 8 (HEX/B28

=

0).

DV - Data Valid, PIN 14.

DV goes to logic 1 when the code corresponding a valid tone pair is present on the data outputs.

ED - Early Detect (CS203 Only), PIN 6.

Indicates data detection prior to processing through the timing circuitry. It is subject to false triggering and drop-outs but can be used to determine if signals are reaching the decoder.

Miscellaneous

N/C -No Connect (CS202 Only), PIN 6.

Not internally bonded.

4-12 DS6F1

~

...

^...,~

... .

.

^..,-~

^{... .}

..,

Semiconductor Corporation

..

^~~

... ^.., CS204

DTMF Receiver

Features General Description

• Full Receiver Implementation

• Central Office Quality

• Detects All 16 DTMF Tone Pairs

• Uses Inexpensive 3.579 MHz Colorburst

The CS204 is a fully integrated DTMF (Dual Tone Multifrequency) receiver that decodes the tone pairs used in standard tone dialing schemes. All of the functions needed for decoding the tone pairs are implemented using Crystal's double-poly CMOS process for low power and high performance.

Crystal

• Hex Output

• Built-in Filter for Dial Tone Rejection

• 14 Pin Package

• Single 5 Volt

±

10% Power Supply

• Low Power CMOS Technology

• Pin Compatible with SSI 204

ORDERING INFORMATION CS204-P 14 Pin Plastic DIP Standard 300 mil DIPs

Block Diagram

r···B~~~~~£IT··l···;

!

I LlMITERSI.--_ _ _ --, ANALOG IN 7

XOUTo-9- - _ - o t

XENo-6 _ _ _ _ _ ~

ATB~11---~

II

^POWER

II

4 8

Vp GND

DIGITAL FREQUENCY DETECTORS

TIMING

3 EN

AUG'S7 DS7F1

Crystal Semiconductor Corporation P.O. Box 17847, Austin, Texas 78760 (512)445-7222 TWX:910-874-1352

•

.. - ^{... _.}

. --- ._ ^.

.., ... -

^CS204

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

DC Supply Vp-GND

-

7.0 V

Input Voltage, Any Pin Except

Yin - 0.5 Vp + 0.5 V Analog in

Input Voltage, Analog In Yin Vp -10 Vp + 0.5 V Input Current, Any Pin _{(Note 1)} I in

-

_±10.0 rnA

Ambient Operating Temperature TA 0 70 °C

Storage Temperature Tstg - 65 150 °C

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal opera-tion is not guaranteed at these extremes.

Note: 1. Transient currents of up to 1 OOmA will not cause latch-up.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Units

DC Supply Vp 4.5 5.0 5.5 V

Crystal Frequency Fc 3.5759 3.5795 3.5831 MHz

Ambient Operating Temperature TA 0 25 70 °C

DIGITAL CHARACTERISTICS (TA = O°C to 70°C· V

.

p = 5V + 10%)

-Parameter Symbol Min Typ Max Units

High-Level Input Voltage V_1H 0.7Vp

-

^{Vp Volts}

Low-Level Input Voltage V1L 0

-

^{0.3Vp Volts}

High-Level Output Voltage 200 uA load (Note 2) V_OH Vp - 0.5

-

^{Vp Volts}

Low-Level Output Voltage

VOL 0

400 uA load (Note 2

-

^{0.5 Volts}

Note: 2. Does not include XOUT.

Specifications subject to change without notice.

4-14 DS7F1

- ... __ ^...

. --- .-.

_ ^.. __ ^...

-ANALOG CHARACTERISTICS (TA

=

O°C to 70°C; Vp

=

5V± 10%)

Parameter Symbol Min Typ

Supply Current Ip

-

^6.0

Frequency Detect Bandwidth BW

±

(1.5r 2Hz/ ±2.3 Detection Amplitude (note 3)

-

^{- 32}

-Twist _{(note 4)}

- ^-

^±10

60 Hz Tolerance

- -

^0.8

Dial Tone Tolerance (note 5,9

- ^-

²²

Talk Off _{(note 6)}

- -

²

Power Supply Noise _{(note 7)}

- -

¹⁰

Noise Tolerance _{(note 6, 9}

- -

^-12

Input Impedance at ANALOG IN Zin 100//15

-(note 8)

CS204

Max Units 12 rnA

±3.5 %of

t

- 2 dBm

-

^dB

-

Vrms

-

^dB

-

hits

-

mVp_p

-

^dB

-

^kohmll _pF

Notes: 3. Each tone. dBm = decibels above or below a reference power of 1 mW into a 600n load.

4. Twist

=

high tone/low tone.

5. Precise dial tone frequencies of 350Hz ± 2% and 440Hz ± 2%.

6. MITEL tape #CM 7290

7. Bandwidth limited (3kHz) Gaussian noise.

S. Vln = (Vp -10V) to Vp

9. Referenced to lower amplitude tone

DS7F1 4-15

•

~

....

^~~~.

.

^~--

^._.

- ^..

^~~

^...

-SWITCHING CHARACTERISTICS (TA = O°C to 70°C; Vp = 5V ± 10%)

Parameter Symbol Min Typ Tone Time:

for detect ton 40

-for reject ton

-

-Pause Time:

for detect toff 40

-for reject toff

-

-Detect Time td 25

-Release Time tr 25

-Data Setup Time tsu

7

-Data Hold Time th

7

9

Output Enable Time (note 10) ten

-

200 C L

=

50 pF, R L = 1 kohm

Output Disable Time (note 10)

~is

-

₁₅₀

C L

=

35 pF, R L

=

500 Ohms Output Rise Time (note 10)

trise

-

₂₀₀

C_L

=

^{50 pF}

Output Fall Time (note 10) tfall

-

160 C_L

=

^{50 pF}

Note: 10. RL and CL are parallel impedances.

4-16

CS204

Max Units

-

^ms

20 ms

-

ms

20 ms

46 ms

50 ms

-

us

10 us

300 ns

200 ns

300 ns

250 ns

DS7F1

~

...

^~

....

. --- ._.

_ ^...

Dans le document o :11 II (Page 117-128)