CS5012 experience permanent damage. If the two

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^--~.

. .,,-- ._.

_ ^.. __ ^...

-A histogram test is a statistical method of deriv-ing an AID converter's differential nonlinearity.

A ramp is input to the AID and a large number of samples are taken to insure a high confidence level in the test's result. The number of occurren-ces for each code is monitored and stored. A perfect AID converter would have all codes of equal size and therefore equal numbers of occurrences. In the histogram test a code with the average number of occurrences will be considered ideal (DNL = 0). A code with more or less occurrences than average will appear as a DNL of greater or less than zero LSB. A missing code has zero occurrences, and will appear as a DNL of -1 LSB.

Integral Nonlinearity

Integral nonlinearity is defined as the deviation of the transfer function from an ideal straight line through zero· and full scale. Even if differential linearity errors are small, they may combine to produce a gross INL error at some point in the transfer function. A unique calibration algorithm, a lack of superpo~ition of errors due to a capacitor based DAe, and low capacitor voltage coefficient keep INL errors below ±1I2 LSB.

+1

_+112 III

CS5012

Clock F eedthrough

Maintaining the integrity of analog signals in the presence of digital switching noise is a difficult problem. The eS5012 can be synchronized to the digital system using the CLKIN input to

~void conversion errors due to asynchronous interference. However, digital interference will still affect sampling purity due to coupling between the eS5012's analog input and master clock.

The effect of clock feedthrough depends on the sampling conditions. If the sampling signal at the HOLD input is synchronized to the master clock, clock feedthrough will appear as a dc offset at the eS5012's output. The offset could theoreti-cally reach the peak coupling magnitude (Figure 14), but the probability of this occurring is small since the peaks are spikes of short duration.

Master Clock Analog Input Clock Feedthrough Int/Ext Freq Source Impedance RMS Peak-to-Peak Internal 2MHz 50 I) 15uV 70uV

External 2MHz SOl) 25uV 110uV

External 4MHz 50 I) 40uV 150uV

External 4MHz 250 25uV 110uV

External 4MHz 2000 80uV 325uV

Figure 14. Examples of Measured Clock Feedthrough

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-I z

0_112

Figure 13. CSS012 Differential Nonlinearity Plot

~-- ~--~--~-- ~--~--~--

---

---If sampling is petfonned asynchronously with the master clock, clock feedtbrough will appear as an ac error at the eS5012's output. With a fixed sampling rate, a tone will appear as the clock frequency aliases into the baseband. The tone frequency can be calculated using the equa-tion below and could be selectively filtered in software using DSP techniques.

f tone ⁼ (Nfs - f c1k )

where N=f clk/f s rounded to the nearest integer

The magnitude of clock feedtbrough depends on the master clock conditions and the source impedance applied to the analog input. When operating with the eS5012's internally generated clock, the CLKIN input is grounded and the dominant source of coupling is through the device's substrate. As shown in Figure 14, a typical CS5012 operating with its internal oscillator at 2MHz and 50n of analog input source impedance wil exhibit only 151lV nns of clock feedthrough. However, if a 2MHz extemal clock is applied to CLKIN under the same conditions, feedtbrough increases to 251lV nns.

Feedthrough also increases with clock frequency; a 4MHz clock yields 40llV nns.

Clock feedtbrough can be reduced by limiting the source impedance applied at the analog input. As shown in Figure 14, reducing source impedance from 50n to 25n yields a l51lV nns reduction in feedthrough. Therefore, when operating the CS5012 with high-frequency external master clocks, it is important to minimize source impedance applied to the CS5012's input.

Also, the overall effect of clock feedtbrough can be minimized by maximizing the input range and LSB size. The reference voltage applied to VREF can be maximized, and the CS5012 can be operated in bipolar mode which inherently doubles the LSB size over the unipolar mode.

DS15F2

CS5012

Power Supply Rejection

The eS5012's power supply rejection petfonnance is enhanced by the on-chip self-calibration and an "auto-zero" process. Drifts in power supply voltages at frequencies less than the calibration rate have negligible effect on the CS5012's accuracy. This, of course, is because the CS5012 adjusts its offset to within a small fraction of an LSB during calibration.

Above the calibration frequency the excellent power supply rejection of the internal amplifiers is augmented by an auto-zero process. Any offsets are stored on the capacitor array and are effectively subtracted once conversion is initiated. Figure 15 shows power supply rejection of the CS5012 in the bipolar mode with the analog input grounded and a 300mV pop ripple applied to each supply. Power supply rejection improves by 6dB in the unipolar mode . Notches of increased rejection arise from the auto-zeroing at the conversion rate. The frequen-cies at which these notches occur also depend on the value of the captured analog input. The line shows worst-case rejection for all combinations of conversion rates and input conditions in the bipolar mode. Again, power supply rejection is 6dB better in the unipolar mode.

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Power Supply Ripple FrequellC)'

Figure 15. Power Supply Rejection

6-21

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. --- ._.

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-Aperture Jitter

Track-and-hold amplifiers commonly exhibit two types of aperture jitter. The first, more appropriately termed "aperture window", is an input voltage dependent variation in the aperture delay. Its signal-dependency causes distortion at high frequencies. TheCS5012's proprietary architecture avoids applying the input voltage across a sampling switch, thus avoiding any

"aperture window" effects. The second type of aperture jitter, due to component noise, assumes a random nature. With only lOOps peak-to-peak aperture jitter, the CS5012 can process full-scale signals up to 112 the throughput frequency without any errors due to aperture jitter.

CS5012

DS15F2

-_ ^.... _ ^...

. ..,-- .- .

...

^CS5012

DS15F2

CAL INTRLV AO RST Function

+ ^{X X X X}

'"

⁰ Hold and Start Convert

X 0 1 X X

*

⁰ Initiate Burst Calibration

1 0 0 X X

*

⁰ Stop Burst Cal and Begin Track

X 0 X 0 X

..

₀ Initiate Interleave Calibration

X 0 X 1 X

*

⁰ Terminate Interleave Cal

X 0 X X 0 I 0 Read Output Data

1 0 X X 0 0 0 Read Status Register

X 1 X X X

*

^X High Impedance Data Bus

X X X X 1

..

_X High Impedance Data Bus

X X X X X X 1 Reset

0 0 X X X 0 X Reset

*

The status of AD IS not cntical to the qlCI"ation specified. However, AD should not .. be low With CS and HOLD low, or a software reset will result.

CSS012 Truth Table

+5V 10(}

Analog < > - - - . . . , . . . - - - . - ' V \ / \ r - . . - - - . . - - - - , Supply

Analog

Signal 0---1 Source

Voltage

-SV

O .... VREF or

±VREF

CS5012

Dans le document o :11 II (Page 182-186)