Tab/e 12. Residue Codes When any of these conditions occur and interrupts
B Bits per Character are enabled, the MPSCC issues an interrupt request.
In addition, if a condition affect vector mode is en.
Previous 2nd Previous abled, the vector generated (and the contents of SR2B
D3 °2 °1 Character Character
for nonvectored interrupts) is different from that of a 1 0 0 CCCCCCCC CCCCCDDD received character available condition. Therefore, it 0 0 CCCCCCCC CCCCDDDD is not necessary to analyze SR1 with each character 1 CCCCCCCC CCCDDDDD to determine if an error has occurred.
0 0 CCCCCCCC CCDDDDDD Also, the parity error and receiver overrun error flags 1 0 CCCCCCCC CDDDDDDD are latched. That is, once one of these errors occurs, 0 C C C C C C C C* DDDDDDDD* the flag remains set for all subsequent characters CCCCCCCD DDDDDDDD until reset by the error reset command. Therefore read 0 0 0 CCCCCCDD DDDDDDDD SR1 only at the end of a message to determine if
7 Bits per Character either of these errors occurred anywhere in the
message. The other flags are not latched and follow
Previous 2nd Previous each character available in the receiver buffer.
03 02 °1 Character Character
1 0 CCCCCCC CCCCCDD Parity Error [Od: This bit is set and latched when 0 0 CCCCCCC CCCCDDD parity is enabled and the received parity bit does not 1 0 CCCCCCC CCCDDDD match the sense (odd or even) calculated from the
0 0 CCCCCCC CCDDDDD data bits.
1 0 CCCCCCC CDDDDDD
Receiver Overrun Error [051 : This error occurs and is 0 1 C C C C C C C* D D D D D D D*
latched when the receiver buffer already contains 0 0 0 CCCCCCD DDDDDDD three characters and a fourth character is completely 6 Bits per Character received, overwriting the last character in the buffer.
Previous 2nd Previous
03 02 °1 Character CRC/Framing Error [Osl : In the asynchronous mode
1 0 0 CCCCCC CCCCCD a framing error is flagged (but not latched) when no 0 0 CCCCCC CCCCCD stop bit is detected at the end of a character (RxO is 1 1 0 cceece CCCOOO low one bit time after the center of the last data or parity bit). When this condition occurs, the MPSCC 0 0 CCCCCC CCDDDD waits an additional one·half bit time before sampling 1 CCCCCC CDDDDD again so that the framing error is not interpreted as
0 0 cecccc DDDDDD a new start bit.
5 Bits per Character In the synchronous mode, this bit indicates the result
Previous 2nd Previous of the comparison between the current CRC result and
03 °2 °1 Character the appropriate check value. It is usually set to one,
0 0 C C e C C* D D D D D* since a message rarely indicates a correct CRC result 0 1 0 ceCCD DDDDD until correctly completed with the CRC check character.
1 0 CCCDD D D D D D Note that a CRC error does not result in a special
0 0 CCDDD D D D D D receive condition interrupt.
0 0 0 CDDDD DDDDD End of HOLC Frame [EOF] [071 : This status bit is used
Notes: C
=
CRC bit only in the bit synchronous mode to indicate that theD
=
Valid data end of frame flag has been received and that the CRC• =
No residue error flag and residue code are valid. This flag can be Special Receive Condition Flags reset at any time by issuing an error reset command.The MPSCC also automatically resets this bit when the The status bits described below-parity error (if parity first character of the next message is sent.
as a special receive condition is enabled), receiver
over-!\fEe
Status Register 2B
0, DO
Interrupt Vector
Interrupt Vector [Do -07 - Channel B Only]
Reading status register 2B returns the interrupt vector that is programmed into control register 2B. If a con-dition affects vector mode is enabled, the value of the vector is modified as shown in table 13.
Code 111 can mean either channel A special receive condition or no interrupt pending. Examine the inter-rupt pending bit (D1 of status register 0, channel A), to distinguish which it means. In a nonvectored inter-rupt mode, the vector register must be read first for the interrupt pending to be valid.
Status Register Bit Functions (Sheet 1 of 2) Control Register 0 Reset EXT/Status Interrupts Channel Reset
Enable INT on Next Ax Character Reset Tx INTfDMA Pending Error Reset
Pointer for the Selection of a Read/Write Register
End of Interrupt (EOI - Channel A only) Null Code
Reset Rx CAe Checker Reset Tx CRe Generator Reset Tx Underrun/EOM Latch
Control Register 1 Rx INT on First Character
INT on All Rx Characters OR Interrupt on (Parity Affects Vector) Special Receive INT on All Rx Characters Condition (Parity Does Not Affect
Vector) Wait on Receiver/Transmitter - Tx Byte Count Enable L - - - W a i t Enable
ItPD7201A
Table 13. Condition Affects Vector Modifications Interrupt
No interrupt pending Channel B transmitter buffer empty
Channel B external/status Change
Channel B received character available Channel B special receive condition
Channel A transmitter buffer empty
Channel A external/status change
Channel A received Character available Channel A special receive condition
v, vo }
l _Jl==~~~~~~~~~~~~V2
- V 5 V3 V4 V6 V7 Interrupt VectorControl Register 2 (Channel AI
I Both Channels Interrupt
o BothChannelsDMA-lnternal PflofityMode 1 BothChannels DMA-External PnontyMode
l
Channel A DMA, Channel B INTSync Character Load Inhibit
" - - - Address Search Mode (HOle)
JLPD7201A
Status Register Bit Functions (Sheet 2 of 2)
Control Register 4
Parity Enable SOLe Mode (0111111 0 Flag) External Sync Mode
L
_~=~====CRC-16ICRC-CCITT RTS Tx Enable Send BreakOTR
Tx5 Bits (or Less)/Character Tx7 Bits/Character
[1) ForSDLC it must be programmed to 01111110 for flag recognition.
Status Register 0
Rx Character Available INT Pending (Channel A Only)
ttiEC
[1] Used with special receive condition mode.
{2] Variable If Status Affects Vector is programmed.
S1a1us Ragistsi 3
NEe Electronics Inc. NEe
Description
TheJlPD72001 advanced multiprotocol serial controller (AMPSC) is a high-performance, single-chip, serial communications controller designed to meet a wide variety of communications requirements. The AMPSC contains two independent full-duplex channels which can be configured to transmit and receive data in either asynchronous protocol or one of two synchronous protocols: character-oriented protocol (COP) or bit-oriented protocol (BOP). The COP and BOP synch-ronous protocols include cyclic redundancy check (CRC) generation and checking.
The AMPSC has several interrupt modes, including vectored and nonvectored. Separate direct memory access (DMA) requests are available for the transmitter and receiver on each channel, allowing high speed operation. The AMPSC is easily interfaced to most microprocessors with a minimum of logic.
The JlPD72001 AMPSC is an upgraded CMOS version of the JlPD7201A MPSCC with the following additions:
four internal baud rate generator (BRG)/timers, two digital phase-locked loops (DPLL), two crystal oscilla-tors, and the capability of synchronous data link control (SDLC) loop operation. The BRG's can be used as independent timers, when they are not being used as baud rate generators. Each timer generates its own zero count interrupt. These features simplify design requirements and at the same time enhance the flexible architecture of the JlPD7201A.
Features
D Advanced version of the JlPD7201 A
D Functional superset of industry standard 8530 D CMOS technology
D Multiprotocol - Asynchronous - Synchronous
- Character-oriented (BISYNC/MONO-SYNC) -.Bit-oriented (SDLC/HDLC)
D Two independent full-duplex channels D Versatile host-system interface
- Software polling - Interrupt -DMA
D I nterface to a majority of microprocessors (V-Series, 8080, 8085, 80X86/88, and others)
D DC to 2.2-Mb/s data rate D Modem control signals
D NRZ, NRZI, and Frill encoding/decoding, Manchester decoding
D Digital phase-locked loop per channel
D Two baud rate generator/timers per channel (receive and transmit)
D Crystal oscillator per channel D Loopback test mode D SDLC loop mode D Mark idle detection D Short frame detection D Single +5 V power supply
D Standby mode for reduced power consumption D Two speed versions: 8 MHz and 11 MHz systems
and input data clocks
D Available in DIP, PLCC, and quadflat packages pPD72001 GC-386 52-pin plastic miniflat 8 MHz pPD72001 GC-386-11 52-pin plastic 11 MHz
pPD72001L 52-pin plastic 8 MHz
leaded chip carrier (PLCC) pPD72001 L -11 52-pin plastic leaded
chip carrier (PLCC)
Pin Configurations