- I BUSY I OBF I IBF

Input Buffer Full

IBF (bit 0) indicates that data is stored in the internal input data buffer during command/parameter input from the host processor. It is set on the rising edge of the WR strobe signal when the host processor writes commands/parameters. It is reset when the input data buffer contents are read by "PD72022 internal process-ing.

"PD72022

The host processor should check that the flag is reset before inputting the next command/parameter. If a command/parameter is input when the flag is set, the

"PD72022 drives the READY signal low, forCing the host to wait.

Output Buffer Full

OBF (bit 1) indicates that the "PD72022 has data stored in the output data buffer. It is set when a write is made to the output data buffer during internal processing. It is reset on the rising edge of the RD strobe signal when the host reads the output data buffer contents through the parameter output port.

The host processor should check that the flag is set before reading data from the parameter output port. If data is read when the flag is set, the "PD72022 drives the READY signal low, forcing the host to wait. The flag is reset when a command is input.

Busy

The BUSY flag (bit 2) indicates that the "PD72022 is performing command processing. It is set under the same conditions as IBF and reset when the execution of all commands stored in the internal FIFO buffer has been completed.

In command processing of SPRRD, SPRWR, BLKrIN, BLKTOT, WDAT, or RDAT, however, BUSY is reset when the FIFO buffer is empty after the completion of process-ing of successive input commands. Therefore, BUSY is always set when any of these six commands is being executed.

Error

ER (bit 4) indicates that an error occurred during com-mand processing. It is set when an abnormal state is encountered; for example, when parameters required for command execution are not entered, or the value of an entered parameter is not proper.

When an error occurs, "PD72022 stops command pro-cessing. To recover, issue the EXIT command, followed by the desired command. ER is reset when the EXIT command is executed.

Specific error causes are as follows.

(1) Parameter is entered when command code is not entered.

(2) Command/parameter is entered from any port other than the command or parameter input port.

(3) Any code other than a command code Is entered from the command port.

3-87

pPD72022

(4) The number of parameters is too large. Up to a given number of parameters are assumed to be valid and processed. When excessive parameters are entered, ER is set and the excessive parameters are not processed.

(5) The number of parameters is too small. All the entered parameters are assumed to be valid and processed.

(a) When a command (except EXIT) is entered fol-lowing the parameters, ER is set and command processing starts

(b) When an EXIT command is entered following the parameters, it is assumed that termination of the immediately preceding command entered is specified. ER is not set and command entry is awaited.

(c) When other than a command or parameter entry follows the parameters, an error results. ER is set and command entry is awaited.

(6) LPNR command is made on any area other than the active screen area specified by the ACTSCR com-mand.

Sprite Control

The SC flag (bit 5) indicates occurrence of sprite over or sprite collision state during sprite display operation. It is updated each time one screen display is terminated (vertical blank).

(1) Sprite Over. The SC flag is set when the number of

ttlEC

sprite images existing on a single horizontal line exceeds the HSPN setup value. The first sprite number exceeding the setup value can be read by command (SPROV) specification.

(2) Sprite Collision. The SC flag is set when dot overlap of two or more sprite images occurs.

Vertical Blank

VB (bit 6) indicates vertical blanking time (B BR, B BL, or VS time). It can be used for the host processor to synchronize with display operations.

Light Pen Detect

LP (bit 7) indicates that an address is detected by using the light pen signal. It is set when the address is detected and reset when the LPNR command is issued.

CONTROL

After initialization (figure 19), the ~PD72022 executes control according to the sequence shown in figure 20.

In figure 20, a check is made to ensure that IBF (bit 0) of the ~PD72022 status data format is cleared to 0; then the command/parameter is written.

If the command is a data read or write command, then data is read or written.

The sequence to check that the IBF bit is cleared to 0 can be omitted by using the READY signals; however, this does not apply to read commands (RDAT, BLKTOT, SPRRD, DPRD, LPNR, SPROV).

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Figure 19. pl'D72fJ22lnitia/izlltion

Display operation mode, scan timing, etc., are set

The display screen layout and display formatar. specified. As required, the active screen area Is selected by using ACTSCR or the cursor display format is specified ... _ _ _ .,... _ _ _ "" by using !he CURDEF command.

The sprite atlribute lable bose address and sprite display format are specified.

Screen conlrol information or sprite allrlbute information is slDred in video memory.

Display dala Is slDred In vIdeO memory.

Screen control labia base address and border color are set and display is initiated.

"PD72022

491"&4828

3-89

"PD72022

Figure 20 PPD72022 Basic Control Row

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DISPLAY

Static Picture Display

The ILP072022 lOP has three static picture display modes: text, semigraphics, and graphics.

Text Mode. Video memory data is recognized as char-acter code and attribute data. Charchar-acter patterns from the character generator specified by character code are displayed. Color or format qualification is specified by attribute data paired with character code. See figure 21.

Semi graphics Mode. Video memory data is recognized as pattern code. Pattern data (format and color) in the pattern data area specified by pattern code is displayed.

Two modes are available according to how pattern data is stored. See figures 22 and 23.

Graphics Mode. Video memory data is recognized and displayed as color patterns corresponding directly to the display screen. See figure 24.

Sprite Image Display

The ILP072022 lOP can control a maximum of 32 sprite images. Collision between sprite images can be de-tected.

Any desired color pattern (sprite) is displayed at any desired position of the screen based on information in the video memory sprite attribute table. Sprite control commands can change the sprite size, color, display address, display position, etc. See figure 25.

Screen Split Display

The ILPD72022 IPO can split the display screen into rectangular windows and display any area extracted from video memory. Each display area is independently controlled by the ILP072022. See figure 26.

t-{EC "PD72022

Figure 21. O.t. Row In liIxt Mode

Display Screen Video Memory

-"1

^nnne

nhne Character lOP

mcolumn memory

~

Attribute data Attribute, meolumn

tJ

Character code

- r-

color specification

A

Character generator

. .,.,...

Figure 22. Dat. RoWin SemlgraphiCIIllode D

Display Screen Video Memory

T

Mode specification nline

Patlerncode lOP

meolumn

~

_MOD ^_L....

I

Color specification

•

^{m column} • A

Pattern code I--

r

-Color speeifi- A

cation

....,....48

3-91

"PD72022

Figure 23. DataRDrIf In Semlgraphics Mode t

Video Memory

T

Mode specification

Pallemcode lOP,

mcolumn

~

^'. MOD

Color specification

Pallerncode

-

-{OJ] ,

^{>---16 color}

FiguTe 24. Data Row in Graphlcsllode

-,

n rasters m dots

~

Video Memory

Graphics memory

,

lOP

Color specification

-'

Display Screen

nline

" -mcolumn

A

-83v0-5925B

Display Screen

n rasters

~I I

f f

t\'EC "PD72022

Figure 25. 0111. Row IJrH'ing Sprite/mage Display

Display Screen Video Memory

YP

Sprite attribute dala

r--'--lOP XP

~

YSIZE

JI

^YP _'

-..--- ^{XSIZE II XP SPDM}

Attribute,

-

^SPDA

S;

color specification Attribute

Display position control

~ II

I

Sprile pattem data

3-93

"PD72022

Figure 26. Example of Screen Split Displey

Video Memory

J:=~==~VW~1:===~~.

VSA1 ~

-t

RSA1 VH1

c::r

t

A";

-L.. _ _ _ Virtual Screen 1 1 V W 3 -VSA3

RSA3

6-L..

Virtual Screen 3

VSA2

RSA2

&--ILnll

L.:: _ _ _

®,

Virtual Screen 2 VH 2

I---i-~

Scan Mode Specification

The I'P072022 lOP enables specification of four scan modes by using SYNC command parameter RM before video signal generation. See figure 27.

Noninterlace Mode.The raster address Is incremented for each horizontal scan. The display data address is updated every specified number of rasters.

In graphics mode, the display data address is updated each horizontal scan.

Interlace Mode. Odd and even fields are displayed alternately. In the odd field, the raster address starts at 0;

in the even field, it starts at 1. The raster address is incremented by two for each horizontal scan.

In graphics mode, the display address is updated so that display data in the opposite field is skipped.

In interlace mode, the MRA value must be specified so

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Display Screen

__ ~I~· __ ~~~0Th~~R_W_1_.2_._3::::::::::::~·1

(RXP 1. RYP 1)

t

ABC RH1

(RXP 2. RYP 2)

~.-." 1

laJl ^{QQ ~,}

"'"_, I

(RXP 3. RYP 3) _Display

-t

_RH3

Real Screen 3

--±.

83vQ·5928B

To use the interlace mode, a value appropriate for the 16-kHz monitor must be set in the raster parameter and the interlace synchronizing signal must be input from an external source.

Vertical Magnification Mode. The raster address is incremented every two horizontal scans. The display data address is updated every specified number of ras·

ters.

In graphics mode, the display data address is updated every two horizontal scans.

Normal Mode. The raster address is incremented each horizontal scan. The display data address is updated every specified number of rasters.

In graphics mode, the display data address is updated each horizontal scan.

NEe

Figure 27. Scan Modes

A. Noninterlace Mode

Dot Position ICG Image]

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

640 x 400 data is displayed on a 24.8-kHz CRT.

B. Interlace Mode

Dot Position ICG Image]

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Odd 0 Even

field ++++++++-+-'-+-+-+-'e-f-+ 1 field

Raster

Address +++-r-~r1-+-+-+~~++-r-r7

+-t-~-+-r+-~r+-r1-t-~-+7 640 x 400 data is displayed on a 15.8-kHz CRT.

"PD72022

C. Vertical Magnification Mode

Dot Position ICG Image]

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

640 x 200 data is displayed on a 24.8·kHz CRT.

D. Normal Mode

Dot Position ICG Image]

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

640 x 200 data is displayed on a 15.8·kHz CRT.

49NR·4758

3-95

"PD72022 t-IEC

ttlEC

NEe Electronics Inc.

Description

The IlPD72120 Advanced Graphics Display Controller (AGDC) displays characters and graphics on a raster scan device from commands and parameters received from a host processor or CPU. Features of the AGDC include high-speed graphics drawing capabilities, video timing signal generation, large capacity display memory control Qncludlng video RAMs), and a versatile CPU interface. These features allow the AGDC to control graphics drawing and display of bit-mapped systems.

Features

Cl High-speed graphics drawing functions

- Graphics drawing: dot, straight line, rectangle, circle, are, sector, segment, ellipse, ellipse are, ellipse sector, and ellipse segment

- Maximum drawing speed

500 ns/pixel (8 MHz, pixel mode) 500 ns/dot (8 MHz, plane mode)

- Area filling (high-speed processing in word units):

triangle, trapezoid, circle, ellipse, and rectangle - Painting: filling of any arbitrary enclosed area (bit

boundary retrieval)

- Data transfers In display memory: multiplane transfers; data transformation (90°/180°/270°

rotation and reversal); multiwlndow transfers;

maximum transfer speed of 500 nS/Word -Image processing: slant, arbitrary angle rotation,

16/N enlargement, and N/16 shrinkage (N any integer from 1 to16)

- Position specification by X-V coordinates - logical operations between planes

eooe8

"PD72120 Advanced Graphics Display Controller

Cl Video timing Signal generation

- High-speed processing by two system clocks:

display (for video sync Signal generation) and graphics drawing clocks

- External synchronization capability

Cl Large-capacity display memory

- Display memory bus Interface: 24-bit address and 16-bit data bus for addressing up to 16M words, 16 bitS/Word

- Video RAM (VRAM) control - Display memory bus arbitration

Cl Host processor (CPU) interface

- System bus Interface: 20-bit address bus, 8- or 16-bit data bus

- Data transfer with external DMA controller: from system memory to display memory (PUT); from display memory to system memory (GET) - High-speed pipeline processing with preprocessor

before drawing processor

- CPU memory or I/O mapping of Internal registers and display memory for efficient system interface

Cl 8-MHz system clock

Cl CMOS technology

Cl Single +5-volt power supply

Cl Packages: 84-pin PLCC, 94-pin plastic miniflat Ordering Information

Part No Package

"PD72120L B4-pln PLCC

"PD72120GJ-5BG 94-pln plastic mlniflat

3-97

"PD72120

Pin Identification

Symbol I/O Signal Function Clock Pi".

ClK In Clock supplied to circuits other than the sync signal generator and display processor. The drawing processor and preprocessor speed depend on this clock frequency.

SClK In Clock supplied to the sync signal generator and the display processor. This clock frequency is determined by the CRT timing requirements:

horizontal sync frequency. number of dots per line. etc.

System Bus Control Pins

ADo-AD15 I/O I/O bus to the CPU consisting of multiplexed

16-bit address and a bidirectional data bus.

In Upper four address bits of the 20-blt address.

In Latches the address on A16"A19 and ADo-AD15 on the failing edge.

In Together with ADo. defines the data access format as shown below. UBE should be tied high when selected by the address input on ADo-AD7' In Enables reading/writlng of display memory

through the AGDC by the host CPU. The display memory address Is generated by the address Input on A16-A19 and ADo-A015 and by the bank register.

Out Activated by the data access request (lIDiWFl) for the AGOC. During the access, the signal may be low. RESET will set the READY line high.

Out Signals an Interrupt from the AGOC.

Out Indicates a requestfordata transfer (PUT/GET) to an external OMA controller. OMARQ will be low after RESET.

In Acknowledgment of OMA request to the AGOC by the OMA controller.

In Initializes operation of the AGOC. The Internal parameter register Is not cleared by RESET Ot Is Initialized by setting data).

OisplBy.IIIIfOI'Y Control Pins

NEe

Symbol I/O Signal Function

OA16-OA23 Out Upper 8 bits of display memory address (the lower 16 bits of the 24-blt address are output on DADo-DAD1sl·

OASTB Out Indicates that a display memory address Is

DWR

present on the falling edge.

Out Defines the dala formal for accessing the display.

RESET sets both pins low.

DUBE DlBE Data Access Format an external device to transfer display data.

HlDAK Out Indicates that the AGDC memory bus (DADo-DAD15 and DA16-DA23 Is In high-impedance state so that an external device can have access to the display memory bus. Set high by RESET.

Iofdeo Timing Signal Related Pins

VS/EXVS I/O When the AGDC operates as the master. VS Is the vertical sync signal output. When the AGOC operates as a slave. the EXVS input initializes the internal vertical sync Signal on the rising edge.

HS/EXHS I/O When the AGDC operates as the master. HS Is the horizontal sync signal output When the AGDC operates as a slave, EXHS Initializes the internal horizontal sync signal on the rising edge.

Display Signal Related Pins BLANK Out Used to blank the display.

l5i/DiS'P Out Set to OT In the OT mode (when using VRAMs) and specifies the data transfer. In the cycle steal mode (VRAMs not used). indicates the display cycle.

GCSR Out Specifies the display of the graphics cursor GWAIT Out Graphics walt signal

Other Pins

Voo +5-volt power supply

GNO Ground

IC Internally connected; leave unconnected

NEe

Pin Configurations I14-Pin PLeC

AD12 ADS AD13 ADs AD14 AD7 AD1S VDD GND Au;

A17 A18 A19 ASTB UBE ClK DADo DADl IC DAD2 IC

0

IC VDD GND SCLK GCSR VSlEXVS HSlEXHS BLANK DT/DISP HLDRQ HLDAK DWR DAD DASTB WAIT GND DLBE DUBE DA23 DA22 IC

"PD72120

49NR-394B

3-99

! g

DADS DAD4 DADs DADs DA07 DADa

DADs

DAD10 DADll DAD12 DAD1S DAD14 DAD15 JC JC GND GND VDD DA16 DA17 DA18 DA19 DA20 DA2l

~~~o CI~»»~<~>~>~>~~

~OCOr-2:l1111::CD~ ... zc .... 0 .... 0 .... 0 .... z

' " N .... 0 " \"II \,1 m ^CD co ^{CD ...., CJ)} 0 CUI...., • en "'" ^{UI N C}

~~~~~m~~~~w~=O~CD....,CJ)UI.""'N~

o

tt~~~~~~~~~~8~~~~~m~mm~~

ODODOOwOOODOOOOOOOOOOODO

('100

»crzz»~~rr ~r~~oo ^{0101~ ~ ~}

° °IOIZIZ

⁰

°lm Z

^{< ~ 0 0 ~ <} ZO ⁰

~~~~OO~~O~~~ ~I m0~ _{m " 0 ~,,~~~}

0

⁰

0 0

AD4 ADll ADs ADl0 AD2 AD9 ADl ADa ADo VDD GND GND WR AD CSDM CSIR GND IC RESET READY INT DMAAK DMARO

,

;!

::i

i

=

C'i

~

10 c

~ ...

o

I\)

~

NEe

"PD72120 Block Diagram

C L K - RESET- VoDG N D

-WArr DMARQ

i5MAAi"<-INT

READY

CSiR-

CSDM-RD WR

ASTB

UBE

ADo·AD15 A16·A19

CPU Interface Un~

Dans le document NEe (IPD) (Page 186-200)