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Figure 2-31 An SRAM cell
the switch matrices. Each wire on one side of a switch matrix can connect to one wire on the other side of the matrix, as illustrated by dots indicating where connections can be established.
Logic Cell Architecture
Logic cell architectures are influenced by routing structures: FPGAs that have routing structures that have many wires and flexible routing (in which a wire can be connected to any other wire) tend to
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Figure 2-32 XC4000 Interconnect
have smaller logic cells with a larger fan-in and more outputs as a ratio of the number of gates in the logic cell. These are typically antifuse FPGAs. FPGAs that have routing structures with fewer wires and designated interconnections tend to have larger logic cells with less fan-in and fewer outputs as a ratio of the number of gates in the logic cell. These are typically SRAM FPGAs.
Antifuse FPGAs may use logic cells with large fan-in and relatively large fan-out because of the availability of wires to transport signals and the availability of fuses, which allow nearly any wire to connect to any other wire. Routing does not pose a problem or limitation. Antifuse FPGAs may use smaller logic cells to increase the efficiency of the logic cells. Small functions do not waste logic cell resources (e.g., a two-input AND gate will not consume a large amount oflogic resources), and large functions can be built up from multiple logic cells. An architecture with small logic cells will enable the user to utilize the full capacity of the device. If a logic cell is too small, however, most functions will require multiple levels of logic cells, with each level incurring a propagation delay as well as a routing delay associated with the wire capacitance and fuse resistance and capacitance. To balance efficiency with performance, antifuse FPGAs may use slightly larger logic cells with multiple outputs that can implement multiple independent functions.
SRAM-based FPGAs typically use larger logic cells with fewer inputs and outputs. These logic cells can implement larger functions without incurring routing delays, which can be more significant because 'of the larger resistance and capacitance of the programmable element. However, because
47
Timing
48
they tend to have fewer outputs as a ratio of the number of gates in the logic cell, they tend to be less efficient for implementing small functions. Again, the trade-off is made between efficiency and performance and is closely tied to the routing architecture.
Figure 2-33 illustrates the logic cells of Actel's ACT3, AT &T's ORCA, Cypress's pASIC380, Xilinx's XC4000, and Altera's FLEX 8000 families of FPGAs. The first two are logic cells of antifuse FPGAs; the remainder are from SRAM FPGAs.
The ACT3 logic cell (logic module, or LM) has eight inputs and one output; there are two types of logic modules: combinational and sequential (one includes a flip-flop, and the other does not). The logic is based on multiplexers, which are universal logic modules (i.e., a 2n to -1 multiplexer can implement any function of n + I or fewer variables, using 0, 1, and the true and complement of the variables as select lines and multiplexer inputs). As such, the modules can implement any of several hundred functions of the inputs. Larger functions can be built by cascading logic cells.
The ORCA logic cells, or programmable function units (PFUs), have 14 inputs and 5 outputs. Each PFU can be configured as four 4-input LUTs (look-up tables), two 5-input LUTs, or one 6-input LUT, which can implement a function of up to 11 inputs. Each PFU has four flip-flops and can be configured for arithmetic circuits or read/write RAM.
The pASIC380 logic cell has 23 inputs and 5 outputs and can implement multiple independent functions for efficiency. The 4-to-l multiplexer ensures that the logic cell can implement any function of 3 variables, and the wide AND gates also allow gating functions of up to 14 inputs.
Exclusive-OR gates, OR gates, and a sum of three small products, as well as counter macros can be implemented. Larger functions can be built by cascading logic cells. All logic cells include a flip-flop.
The XC4000 CLB has 13 inputs and 4 outputs. It is a complex cell: two 4-input lookup tables (LUTs) feed another 3-input LUT. Each CLB can implement anyone function of four or five variables and some functions of up to nine variables. Alternatively, a CLB can be configured to implement two functions of four variables, or one of two variables and another of five. Each CLB has two flip-flops. The CLB can also be configured for special arithmetic circuits, such as a two-bit adder with carry-in and carry-out, or as a read/write RAM of 16 bits for storing data.
The FLEX 8000 architecture may be considered a hybrid CPLDIFPGA architecture. It addresses the SRAM routing issues differently. In this architecture, the logic cells (logic array blocks, or LABs) are made up of eight logic elements (LEs). Each LAB has a local interconnect in which any LE can connect to any other LE. The local interconnect and the relatively large size of the LABs reduce the routing congestion on the inter-LAB and 110 routing channels. Each LE has a four-input LUT and can implement a single function' of four variables. An LE also has carry circuitry for arithmetic circuits, as well as a flip-flop.
Timing for designs implemented in FPGAs cannot easily be predicted for any but the simplest of designs. Signal propagation delays are a function of the number of cascaded logic cells, the signal path in the logic cells, the number of programmable interconnects through which the signal propagates (as well as the technology, antifuse or SRAM), fan-out, and 110 cell delays. Without a priori knowledge of the value of each of these variables (how many logic cells, number of programmable interconnects, fan-out, etc.)-that is, without a knowledge of how the design will be placed and routed-the propagation delays and system performance cannot be predicted with precision. This is not unlike the dilemma faced when developing a semi-custom gate array. For
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Figure 2-33 The logic cells of several FPGAs
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Logic Function
Logic Function
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Xilinx XC4000 Figure 2-33 (continued)
systems that do not have high-performance requirements, any FPGA will potentially meet performance requirements.
Having an understanding of the technologies as well as the routing and logic cell architectures can help a designer choose an FPGA for a particular application. Additionally, HDLs like VHDL and Verilog allow relative design independence, permitting a designer to benchmark design performance from one architecture to the next without reentering a design.