We've examined behavioral and structural architectures, and we created five different design descriptions for the same function (a 4-bit comparator). We can think of a couple of other
descriptions for a 4-bit comparator, and you may be able to as well. All of these descriptions for the same function demonstrate the flexibility of VHDL, but this flexibility begs the question, "How does the synthesis and fitting of one design description differ from another?" That is, will different PLD
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Figure 3-4 Hierarchical schematic representation of Listing 2-8
resources be used depending on which description is synthesized? For example, if you want the four-bit comparator to be realized in a 22VlO, will the same 22VlO device resources be used regardless of which description is synthesized?
Fortunately, for simple design descriptions (such as those for our 4-bit comparator), almost any description will most assuredly be realized with the same device resources. However, this is not true of more complex design descriptions. The synthesis software must interpret complex design descriptions and create minimized logic equations for your circuit. The synthesis software as well as the place and route (or fitter) software must then determine how to implement those minimized logic equations to make the best use of available resources in the target logic device.
Different design descriptions for complex designs can result in different device resources being utilized for three reasons: (1) The VHDL code may not accurately describe an optimal function. For example, it is possible to describe a design that produces a functionally correct circuit, but which has unneeded logic that is accurately synthesized from the VHDL code. (2) The synthesis software may perform poorly in synthesizing a design description to make the best use of a device's architectural resources. For example, some synthesis software produces sum-of-products logic equations and passes those equations to the placer and router (or fitter) without having optimized the logic for the target architecture. Sum-of-products equations cannot easily be mapped to just any architecture (FPGAs in particular). Therefore, if the synthesis software does not present (to the place and route software) logic in a form that is representative of a device's architectural resources, then more resources than necessary may be used, unless the place and route software can compensate for the
lack of optimization in the synthesis tool. In this scenario, the VHDL description that more closely resembles a netlist of RTL (register transfer level) components representative of device resources will synthesize to a more optimal implementation (provided that the designer reduced the logic). (3) The place and route software (fitter) may not make the appropriate choices for using device resources. If the appropriate heuristics are not embedded within the fitter software, then the fitter may not find a solution for fitting a design as appropriate even though the synthesis software has presented optimized logic and there is a theoretical solution for fitting the design. In summary, different design descriptions can produce different, but functionally equivalent, design equations resulting in different circuit implementations. Mature VHDL synthesis tools should, however, produce nearly equivalent circuits. In the pages to follow, we will point out where there is danger in freely describing logic.
Used to implement hierarchical designs, a structural methodology is also sometimes used to instantiate device-specific resources. Most synthesis tools or silicon vendors provide libraries in which you can instantiate components that represent resources that are available in a device's architecture. Most synthesis tools provide directives or attributes to indicate that such structures are not to be optimized. In other words, software will implement these portions of a design exactly as the structure of the component and how it is connected. This provides the designer with the most control over design implementation.
This type of design methodology should be avoided for several reasons, unless it is the only way to access a required feature of a device. Instantiating device-specific components eliminates the device independence of the design. (The design can remain independent only if the device-specific component has an associated architecture that can be synthesized to logic for other architectures.) U sing such components should be the exception-it should not be necessary to create an entire design from such components. Creating a design from such components requires an inordinate amount of time; it provides little, if any, benefit over schematic-based design entry, and it requires that you build functions from small-device resources. Additionally, you may inadvertently create logic that is not optimal for the architecture or that is in error. It can be an arduous task to find a logic error in a convoluted netlist. This is a design methodology that VHDL seeks to avoid and is precisely why the HDL synthesis markets are growing. Computers can run through algorithms much faster than any human. Carefully constructed software algorithms can produce optimal implemeritations.
We return to the trade-off discussed in the introductory chapter: meeting design requirements versus controlling a design's implementation. In the chapters ahead, we'll identify how circuits will be realized in logic devices to give you an idea as to when it will be most suitable to use behavioral or structural design styles. For the most part, you will want to start out with behavioral design descriptions because they are usually the quickest and easiest way to describe designs. If after synthesizing the behavioral design description, the design implementation meets your performance and cost requirements, then you have completed your design in the shortest possible design time. If at that point you have I!ot met your requirements, then you will want to use the timing or constraint-driven directives available from the synthesis and place and route tools to help achieve the requirements. If the desired results are still not achieved, you can introduce RTL descriptions to optimize critical portions of your design. On your next design, you will be more cognizant of what portions of your design to describe with the different coding styles. As the state of the art in VHDL synthesis improves, you'll be able to describe a larger percentage of your designs completely behaviorally with the appropriate amount of structure.
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