SYSTEM MEMORY
8
MWR
M(R(X))
_______________________________________ 75
CPU CDP1802
TPB NO
8 DATA BUS 0-7
5082-7340
CD4050
,
4 CD4050,
45082-7340
Fig. 92 - Direct selection of I/O devices - one pair of output display digits.
M address, M byte operation comments
I I
I I I nitialize registers
I I I and display I
I I I
0018 3C BN1 Loop here until
18 I switch "ON"
I I Le_. EF1 goes low_
I I i
I Code to perform
I
I count function
I
I I
61 Output 1 Output the counter byte to display.
30 BR Branch to M(0018).
18
Fig. 93 - Portion of a two-digit decimal counter program.
OUT IN
TPB .J"l... CLOCK ,
D8DATf~ADY
SR:r
EU
8t
CLOCK SR
- -
CS1r-
CS1~ CPU NO~ CDP1852 CDP1852
SYSTEM CS2
I r-
CS2MEMORY
-
CDP1802- -
-MRD MODE CLEAR MODE CLEAR
:'-0-N1 V~D B
t ..
8 tm
8 ~
0
)
M(R(X)) 8
J ..
8 DATA BUS 0-7
Fig. 94 - Direct selection of I/O devices - one input and one output port.
76 _--, _ _ _ _ _ _ _ _ _ _ _ User Manual for the RCA CDP1802 COSMAC Microprocessor
line detennines direction of data flow. During an input instruction execute, the CPU is in a memory write cycle with MRD high, i.e., the input register is enabled to the opera-tion; hence, instruction 69 selects port I, 6A selects port II, and 6C selects port III. The user's strobe will activate lines, depending on the chosen instruction. Instruction
61 selects digit pair DO, 62 selects pair DI, and 64 strobed in on a leading edge of the clock pulse when the input is enabled. NO and a read level on MRD will enable data from the bus into output register #1 while the input register #1 is disabled from the bus. A valid byte is strobed from the bus into the output port at TPB. Dur-ing an input instruction, a high level on MRD enables the input port #1 to the bus. Similarly, Nl controls I/O
Fig. 95 - Direct selection of I/O devices - three input ports.
INSTRUCTION 61 SELECTS DIGIT PAIR DO
1
INSTRUCTION 62 SELECTS DIGIT PAIR 01
INSTRUCTION 64 SELECTS DIGIT PAIR 02
1
Fig. 96 - Direct selection of I/O devices - three pairs of output display digits.
Interfacing and System Operations
______________________________________ 77
Programmed I/O - One-level I/O System The I/O interface systems described so far are appli-cable for small systems (up to three I/O ports) where the N lines can be used directly to select or control I/O de-vices. If more than three I/O devices are required, the N lines can be decoded to specify up to 1 of 7 different I/O ports or channels. Fig. 98 illustrates this approach. If line 1 is selected from the decoder, for instance by exe-cuting input instruction 69, the input register is enabled to the bus because MRD is high during memory write output instruction, 61, but
MRD
is low during memory read cycle, disabling the input register from the bus. At lines. If the interrupt is asserted, the two state<ode lines SCQ and SCI are both high, acknowledging an interruptFig. 97 - Direct selection of I/O devices - one of three input ports or one of three output ports.
Fig. 98 - Selection of I/O devices by one-level decoding - one of seven input ports or one of seven output ports.
78 _ _ _ _ _ _ _ _ _ _ _ _ _ User Manual for the RCA CDP1802 COSMAC Microprocessor
Programmed I/O - Two-Level I/O System
The COSMAC architecture imposes no theoretical limits on the number of I/O ports which the CPU can accommodate. Systems larger than those discussed up till now, however, require an additional level of de-coding.
Fig. 99 shows one possible implementation of a large I/O system which handles 256 input and 256 output ports. A 61 instruction is first executed to place an 8-bit device-selection code in the I/O device-select register.
Subsequent execution of a 62 instruction will send an 8-bit control code to the selected output port or chan-nel. Control codes can be used to start or stop electro-mechanical devices, set up specific modes of operation, etc. When the 8-bit I/O device-select register specifies an output device, execution of a 63 instruction will cause the transfer of an output data byte to the selected device.
After an input device is selected, a 6A instruction could be executed to obtain a status byte from
it
selected device. Subsequent execution of a 6B instruc-tion could store an input byte in memory. The
The above examples under "I/O Interface" indicate
1/4 CD4019
Fig. 99 - Selection of I/O devices by two-level decoding - one of 256 input ports or one of 256 output ports.
Interfacing and System Operations - - - -______ 79
The I/O examples described above require that a pro-gram periodically sample I/O device status. These tech-niques also require several instruction executions for each I/O byte transfer. In many cases it is desirable to have I/O byte transfers occur without burdening the program or to transfer data at higher rates than possible with programmed I/O. A built-in direct-memory-access (DMA) facility permits high-speed I/O byte transfer operations independent of normal program execution.
During DMA operation R(O) is used as the memory address register and should not be used for other pur-poses. Two lines, DMA-IN and DMAOOOT, are used to request DMA byte transfer to and from the memory.
Also, a specific code is provided on the state code lines (SCO, SCI) to indicate a DMA cycle (S2).
DMA-IN ACTION during an instruction execute cycle (SI), then the DMA cycle (S2) will follow immediately after SI. If the subsequent S2 cycles will store input bytes in sequential memory locations. S2 cycles do not alter the sequence of program execution. The program will, however, be slowed down by the S2 cycles that are "stolen". The concurrent program must, of course, properly use R(O)
BUS-+ M(R(O)); R(O)+1
M(R(O)) -+ BUS; R(O)+1
and memory areas in which input bytes are being stored.
It may examine R(O) and the memory area involved to observe the course of the data transfer. The program must also set R(O) to the address of the desired first input byte location in memory before permitting a DMA input operation.
Fig. 100 -Implementation of DMA-IN operation.