The COSMAC Microprocessor CDP1802 has an internal oscillator that works with a crystal connected between the CWCK and XTAL terminals. If desired, however, an external oscillator may be used and fed into the CLOCK input. If an external oscillator is used, no negative-going transition of the clock (pause mode). Output sig-nals are held at their values indefinitely. This state is useful for several purposes. Using the WAIT line, the CPU can be easily single-stepped for debugging purposes or, if stopped early in the machine cycle, the CPU can oscillator. DMA's and Interrupts are not acknowledged in the Pause mode.
Fig. 83 -Interface for a mixed ROM/RAM system.
single-phase clock may be used so long as the rise and fall times of the clock pulse are less than 15 micr6-seconds. Each machine cycle consists of eight clock pulses, and each instruction requires two or three machine cycles. Thus, with a 6.4-MHz clock frequency, a machine cycle of 1.25 microseconds could be achieved, and instructions would be executed in 2.5 to 3.75 micro-seconds depending on the instruction.
During normal operation, the CLEAR and WAIT lines are both held high. A low level on the CLEAR line will put the machine into the reset mode with I, N, X, P, Q, Data Bus
=
0, and IE=
1. Actually, X, P, and R(O) are reset during a special SI cycle (not available to the pro-grammer) immediately following transition from the reset mode to any of the other modes (load, run, or pause). The clock must be running to effect this cycle.If the CLEAR and WAIT lines are both held low, the machine enters the load mode. This mode allows input bytes to be sequentially loaded into memory beginning at M(OOOO). Input bytes can be supplied from a key-board, tape reader, etc., by way of the DMA facility.
This feature permits direct program loading without the use of external "bootstrap" programs in ROM's.
Fig. 84 shows one circuit using standard devices from the CD4000 series for controlling the run and load completed, depressing the reset and then the run buttons will start program execution at M(OOOO) with R(O) as the program counter (after one machine cycle). If a DMA request is present when the run switch is turned on, the machine will go into the DMA state immediately with R(O) as the program counter. The user should therefore inhibit DMA externally until the program has changed to a program counter different from R(O).
Interrupts, however, are disabled until the first instruc-tion or DMA request is executed. This delay allows the programmer to place instruction 71 and 00 in the first two memory bytes to inhibit interrupts until he is ready for them. The combined effect of the two instructions is to set IE = O. Interrupts must not occur, however, when the machine is in the load mode because they will force the machine into an anomalous running state. Fig. 85
Interfacing and System Operations
- - - -__________________________ 71
+
+
WAIT
+
CPU CDP1802 +
CLEAR
CD 4012
.---1_--1_--.--1 CLOCK
20 pF /"T"'
...L 22 Mn
D
.---4_--4 _ _ 1--1 XT AL 20 PF - r
Fig. 84 - Simple control interface for CDP1802 microprocessor.
shows the sequence of events and states involved in loading and running a program.
Another circuit that can be used for single-stepping the microprocessor (one machine cycle per switch de-pression) is shown in Fig. 86. This capability is often useful as a debugging aid.
Fig. 87 provides a summary of the modes discussed, the control levels, and the characteristic features of these modes. It is. evident that the run mode can be entered from either the reset or the pause mode.
o 2 3 4 5 6
CLOCK
o
I/O Interface
The three basic ways in which the CPU can com-municate with I/O devices are programmed I/O, inter-rupt I/O, and Direct Memory Access (DMA). In the programmed I/O mode, all data transfer is controlled and timed by the program. In the interrupt I/O mode, the CPU responds to an I/O generated Signal. In the
2 3 4 5 6 7 0 1
___ ITLfULJLf'L
CLEAR ---,~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
WAIT
'--______________ -.J
NOTE 1
TPA~ _ _ _ _ _ _ _ _ _ _
...IIl .... ____ _ __________ r
CPU OUTPUT
TO DATA
~ ~=-==0'I ~
BUS ~---Jlj""""~
MA~~ ____________________ M_(~OO~O~O) ________________ ~~~~M~(O~OO~O~) __________ _
DMA·IN L..o-_ _ _ _ _ _ _ _ _ _ _ _ ~r
==~
RUN
+
RESET_ ... r1~---'L=-:O"-A~D-"-M;.:;O.::.D.::.E---••t
RESETL
RUN _ _MODE MODE MODE
r -
MODEE22a
UNDEFINED~ OFF - High-impedance state
Note 1 - In the Load Mode, TPA pulses are generated only during DMA cycles.
Fig. 85 - Timing diagram for load and run sequences.
72 _ _ _ _ _ _ _ _ _ _ _ _ User Manual for the RCA CDP1802 COSMAC Microprocessor
CPU CDP1802
TPB
Xl~---1C112 C04013 112 CD4001 Q
o +
R VCC
WAIT~---~
TPAr---~
Fig. 86 - Circuit for single-stepping the CDP1802 microprocessor.
MODE CLEAR WAiT OPERATION
RESET 0 1 I, N, X, P = 0, R(O) =0, Q= 0, BUS = 0, IE = 1; TPA and TPB are suppressed;
CPU inS1.
RUN 1 1 CPU starts running one machine cycle after CLEAR is released. Execution starts at M(OOOO) , or an S2 cycle follows if DMA was asserted. I nternal sampling of interrupt is inhibited during initialization cycle.
RESET 0 1 As above.
LOAD 0 0 CPU in IDLE. An I/O device can load memory without "bootstrap" loader.
PAUSE 1 0 Clock:~stops internal operation.
CPU outputs held indefinitely. Permits stretching of machine cycle to match slow devices or memory cycles. DMA and INTERRUPTS not acknowledged.
RUN 1 1 Clock:...J"l.. _ _ _ _ _ _ _ _ _ ~
Resume operation
Fig. 87 - Truth table for mode control of CDP1802 microprocessor.
~o~
CLOCK XTAL
8 MA7 BUS 7 B
MEMORY ADDRESS DATA BUS
MAO BUS 0
Q QOUTPUT
- N2 3
SINGLE
MWR N1 I/O COMMAND
CPU -NO
CDP1802 EF4 EF3 4
I/O FLAGS
MRD -EF2
EF1
DMA·IN 3
OM A-OUT I/O REQUESTS
- - INT
WAIT 2
SC1
SCO STATE CODE
- - 2
CLEAR TPB
>
TPA TIMING PULSES
VSS VCC Voo
1 1 1
Fig. 88 - Summary of interface lines provided by CDP1802 microprocessor.
Interfacing and System Operations _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 73
DMA mode, a direct high-speed data channel- is estab-lished between memory and I/O device. The I/O device
"steals" execution cycles from the CPU and transfer data during these time slots.
Fig. 88 gives a summary of the interface lines pro-vided by the CDP1802 microprocessor. The large number of dedicated lines available offers both economy and flexibility in I/O system designs.
The following paragraphs indicate a few ways in which I/O data transfer can be accomplished under the three basic modes of operation. Throughout these exam-ples, IC's from the CDP1800 and CD4000 series of stan-dard parts are used. Devices from the 1800 series belong to a growing family of dedicated parts designed specifi-cally to interface with each other and with the CDP1802 Microprocessor for optimum system design. A broad choice of standard parts from the 4000 series is also available for flexible and inexpensive system operations.
For detailed information on these devices, the reader should refer to the latest RCA Integrated Circuits DATABOOK.
Programmed I/O - Direct Selection of I/O Devices the EFI flag. The 3C instruction executes a short branch
MEMORY Tele-type* output relay. The opening and closing of this relay contact represent the bit-serial teletype character code.
A . COSMAC program could interpret the sequential states of the
EF1
line to provide an extremely simple bit-serial interface. (The Terminal Interface card and the Utility Program described in Manual MPM-203 give aWhen a low is detected on EF1, the program branches to an input instruction 69 (I
=
6 and N=
9). During execu-tion of 69, the three N bits available at the interface are valid. The NO line, which was low, is active high during the execute cycle. When the CPU responds with an input instruction and the NO line goes high, the input byte is enabled onto the data bus.During this machine cycle, the CPU generates a low byte is entered per strobe pulse.
The input byte might be the byte output of a paper-tape reader, keyboard, or other input device. The
input-*Registered trademark, Teletype Corporation.
74 _ _ _ _ _ _ _ _ _ _ _ _ _ User Manual for the RCA CDP1802 COSMAC Microprocessor con-trol. If a 61 instruction is executed, the NO line becomes high during the execute cycle and can be used with the
put display device. Each HP5082-7340 display chip con-tains a 4-bit register, a decoder, and a hex LED display.
During the execution cycle of instruction 61, when the NO bit is valid, TPB will strobe valid data into the two-digit hex display.
A COSMAC program can be written to simulate a free-running two-digit decimal counter. Each two-digit count can be placed in the output display of Fig. 92.
The switch in Fig. 89 can be used to start and stop the counter. If the switch is in the "ON" position, counting proceeds (00-99). When the switch is turned off, count-ing stops and the current value of the count is displayed.
Turning the switch "ON" again will re-initiate counting, starting at the value displayed. A portion of a possible
"counter program" is shown in Fig. 93. In this example, the logic in Fig. 92 must be modified with the
1VmD
line to distinguish between input and output instruc-tions, as discussed in the material following.
One input and one output port. Fig. 94 shows how
Fig. 91 - Direct selection of I/O devices - one output port.