HANDSHAKE I/O SUBSYSTEM

The handshake 1/0 subsystem involves ports Band C, STRA input, STRB output, and the PIOC register. The following paragraphs explains the strobe and handshake protocols and the detailed operation of the PIOC register.

There are three primary modes of operation for the handshake 1/0 subsystem. The first (default) mode of operation is the simple strobe mode, which uses port B as a simple strobe output port and port C as a simple latching input port. The second mode of operation is a full-input handshake; the third mode is a full-output handshake. In the full-handshake modes of operation, port B is not involved; therefore, it defaults to being a general-purpose output port.

If the application does not require handshake functions, these functions can generally be ignored. Ports Band C can be used for simple general-purpose 1/0; in fact, the STRA and STRB pins can even be used for limited nonhandshake functions. When handshake func-tions are being used, it is usually possible to use any port C pins, which are not needed for handshake, as general-purpose 1/0 pins without interfering with the handshake functions • of the other port C pins. The one exception to this possibility is that while full-output handshake is specified, port C pins cannot usually function as general-purpose input pins.

Examples of mixed use of port C pins is presented in 7.4.5 Nonhandshake Uses of STRA and STRB Pins.

7.4.1 Simple Strobe Mode

The simple strobe mode for the handshake 1/0 subsystem is selected by HNDS equal to zero in the PIOC register. At reset, HNDS is forced to zero, which is the default mode of operation for the handshake 1/0 subsystem. In this mode, the OIN and PLS control bits in PIOC have no meaning or effect.

In simple strobe mode, port B is used as a strobe output port in conjunction with the STRB output pin. Port C is simultaneously used as a latching input port in conjunction with the STRA input pin. The strobe output function at port B is independent of the latching input function at port C.

Figure 7-25 shows the idealized timing for simple strobe mode operations in the MC68HC11A8. The timing for the MC68HC24 is slightly different because the MC68HC24 does not have access to the internal PH2 clock of the MC68HC11A8. Detailed descriptions of the strobe A and strobe B pins are presented in 7.3.3.2 SPECIAL CONSIDERATIONS FOR STRB ON MC68HC24 PRU and 7.3.5.2 SPECIAL CONSIDERATIONS FOR STRA ON MC68HC24 PRU.

7.4.1.1 PORT B STROBE OUTPUT. In response to a write to PORTB, data is changed at port B, and then a two E-cycle pulse is generated at the STRB pin. Although the INVB

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Figure 7-25. Idealized Timing for Simple Strobe Operations

control bit in PIOC allows a choice of polarity for strobe B pulses, Figure 7-25 only shows the INVB equals one case, which selects active-high strobe B pulses.

7.4.1.2 PORT C SIMPLE LATCHING INPUT. Data at port C is required to be valid for a short setup time before and a short hold time after the selected edge on the strobe A pin.

Since the edge on strobe A is asynchronous, it need not have any special relationship with the E clock. The internal STAF bit, which indicates that port C data has been latched, must be synchronized with the internal clocks to avoid setting the flag in the portion of a cycle where it could be read. This factor implies there may be a delay between when the actual port C data is latched and when the MCU becomes aware of it. Not counting internal propagation delays, the MC68HC11A8 would have a delay between zero nanoseconds and one E-clock period. If the relationship between the strobe A edges and the E clock is known, the user can predict the delay between port C data latching and setting STAF by a careful study of the strobe A pin description.

7.4.2 Full-Input Handshake Mode

Full-input handshake mode is selected when HNDS is one and OIN is zero. In this mode, the strobe B output acts as a ready signal to an external system. The external system should not attempt to strobe data into port C until the strobe B signal has been asserted, indicating a ready condition. The strobe A input is an edge-sensitive latch command, allowing the external system to asynchronously latch information into port C.

When a ready condition is recognized, the external device places data on the port D inputs, then pulses the strobe A input. The active edge on strobe A latches data into the PORTCL

register, sets STAF (optionally causing an interrupt). and deasserts strobe B. Deassertion of strobe B automatically inhibits the external system from strobing any new data into port C. Reading the latched data from PORTCL (independent of clearing STAF) causes strobe B to be asserted, indicating new data may now be strobed into port C.

Control bits allow flexibility to adapt to the requirements of a particular application. The INVB control bit selects the polarity of the strobe B signals. The EGA determines whether rising or falling edges will be the active edges for the strobe A input. The PLS bit determines whether strobe B will operate in pulsed mode or interlocked mode. In the interlocked mode, strobe B is asserted when the PORTCL register is read and is deasserted when an active edge is detected at the strobe A input. In the pulsed mode, strobe B is asserted when the PORTCL register is read but only remains asserted for two E-clock cycles.

Figure 7-26 illustrates the full-input handshake protocol. Separate waveforms are included to clarify the pulsed versus interlocked modes of strobe B. Although the polarity of strobe B and the active edge for strobe A can be selected, the figure only shows the case where INVB and EGA are ones. This configuration specifies strobe A to be sensitive to rising edges and the active level on strobe B to be high. The timing shown in Figure 7-26 is the idealized timing for the MC68HC11A8. The idealized timing for the MC68HC24 port re-placement unit has small differences, which do not concern most users.

7.4.3 Full-Output Handshake Mode

Full-output handshake mode is selected when HNDS and OIN are ones. In this mode, port C is used to output data to some external system. The strobe B output signal indicates that port C data is ready for the external system. The strobe A input is pulsed by the external system to acknowledge that it has accepted the data on port C. In the three-state variation of output handshake, strobe A aiso acts like the output enable of a 74HC244 buffer.

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Figure 7-26. Idealized Timing for Full-Input Handshake

•

Figure 7-27 illustrates the full-output handshake protocol. This figure shows strobe B wave-forms for both interlocked and pulsed modes. Wavewave-forms are also provided to show the three-state variation of the output-handshake protocol. Although the polarities for strobes A and B are software programmable, only the case in which EGA and INVB are ones is shown. This case specifies strobe B is active high, strobe A responds to rising edges, and the active level on strobe A is low for the three-state variation of output handshake.

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Figure 1-21. Idealized Timing for Full-Output Handshake

1.4.3.1 NORMAL OUTPUT HANDSHAKE. In an output-handshake transaction, data is out-put to port C pins by writing to the PORTCL register, which automatically causes strobe B to be asserted. The external system recognizes this strobe B signal as a ready indication.

After accepting the data from port C, the external system pulses the strobe A input to acknowledge the receipt of data. The active edge on strobe A causes strobe B to be deasserted and STAF to be set. STAF signals that the MCU can begin the next transaction by writing the next byte of data to PORTCL.

1.4.3.2 THREE-STATE VARIATION OF OUTPUT HANDSHAKE. The three-state variation of output handshake can be thought of as if a 74HC244 buffer had been placed in series with the port C outputs with its output enable connected to the strobe A signal. The transaction sequence is identical to the normal output handshake protocol previously described.

Port C pins, which are to act as three-state outputs, have their corresponding DDRC control bits cleared to zero. As long as the strobe A input is at its inactive level, all port C pins obey their corresponding DDRC specification. When strobe A goes to its active level, all port C pins act as driven outputs, regardless of their corresponding DDRC specification.

The active level is automatically specified when EGA is selected. If EGA is zero, falling

edges are selected and the active level is high. If EGA is one, rising edges are selected and the active level is low. The relationship between the active edge and the active level at strobe A was chosen so that the active edge will correspond to the trailing edge of a port C output enable pulse to strobe A.

7.4.4 Parallel 1/0 Control Register (PIOC)

The PIOC register is used to configure and control the handshake I/O subsystem in the MC68HC11A8. The following register and paragraphs describe each ofthe control or status bits in greater detail.

STAF STAI 1 CWOM 1 HNOS

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This status flag is a key element of the handshake I/O subsystem. Independent of the strobe or handshake mode, STAF is always set as a result of a selected active edge at the STRA pin. The edge at STRA, which is asynchronous to the MCU E-clock, causes data to be asynchronously latched into the PORTCL register. The STAF bit is synchro-nized to the internal PH2 clock. Provided the asynchronous edge occurs at least a setup time before the rising edge of PH2, STAF will become set at that PH2 rising edge. If this setup time is not met, then STAF would not be set until the next PH2. The rising edge of PH2 corresponds to the center of the E-clock low time. The active edge at STRA is software selectable by the EGA bit in the PIOC register.

The STAF bit is cleared by a two-step, automatic clearing sequence. The first step arms the clearing mechanism; the second step clears STAF to zero. To arm the clearing mechanism, software reads the PIOC register while the STAF bit is set to one. The second step depends upon the strobe or handshake mode in effect. In simple strobe mode (HNDS = 0), the second step of the clearing sequence is to read the PORTCL register. In full-input handshake mode (HNDS=1 and OIN=O), the second step ofthe clearing sequence is to read the PORTCL register. In full"output handshake mode (HNDS = 1 and OIN = 1), the second step of the clearing sequence is to write to the PORTCL register. The handshake mode can be changed between the arming and clear-ing steps of this sequence. If the mode is changed, the action required for the second step of the clearing sequence is governed by the state of HNDS and OIN at the time the second step is performed. Although any amount of delay is permitted between the two steps of this clearing sequence, it is best to keep the steps as close together as possible. The arming mechanism is automatically cleared whenever the selected edge is detected at the STRA pin. If an edge is recognized after the arming step but before the clearing step, the internal arming signal will be deasserted, and the clearing step will not clear STAF.

STAI- Strobe A Interrupt Enable

This control bit determines whether STAF will cause interrupts. When STAI is one, a hardware interrupt request is generated whenever the STAF bit is set. When STAI is zero, STAF interrupts are inhibited.

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CWOM - Port C Wired-OR Mode

This bit is used to configure all port C outputs for wired-OR operation. When CWOM is zero, port C outputs operate as active push-pull drivers. When CWOM is one, the P-type pullup devices are disabled, causing port C outputs to act as open-drain drivers.

The CWOM bit simultaneously affects all eight port C bits. The P-channel device forms a P-N junction between the VDD supply and the output pin so that the pin cannot be pulled more than a diode drop above the VDD supply. For this reason, the wired-OR mode cannot be used for level conversion the way open-collector TTL devices are sometimes used.

In a TTL system, a brief contention between two push-pull drivers, though not good practice, generally has no serious consequences. In a CMOS system, a brief contention between push-pull drivers can induce destructive latchup. In cases where two CMOS output drivers could be in contention, they should be configured for wired-OR oper-ation. If there is a brief contention between the time one driver is turned on and the other is turned off, there will be no danger of latchup damage.

HNDS - Handshake/Simple Strobe Mode Select

When HNDS is zero, the simple strobe mode is selected. In the simple strobe mode, the STRB pin is pulsed for two E-clock cycles after each write to port B. Also, port C data is asynchronously latched into the PORTCL register each time the selected edge is detected at the STRA pin. When HNDS is set to one, either full-input or full-output handshake mode is selected. All full-handshake modes use port C, the STRA strobe input pin, and the STRB handshake output pin. Since the handshake I/O subsystem does not use port B when a full-handshake mode is selected, port B defaults to being a general-purpose output port.

OIN - Output/Input Handshake Select

This bit has no effect unless HNDS is one. When HNDS is one, OIN further qualifies the handshake mode. When OIN is one, full-output handshake is selected. When OIN is zero, full-input handshake is selected.

PLS - Strobe B Pulse Mode Select

This control bit determines whether the STRB pin is configured for pusled or interlocked operation. In interlocked mode, once STRB is asserted, it will remain active until an acknowledge edge is detected at the STRA pin. The interlocked mode is selected when PLS is zero. Interlocked mode cannot be specified unless HNDS is logic one. In pulsed mode, STRB is deasserted exactly two E-clock cycles after it is asserted. When the simple strobe mode is selected (HNDS = 0), the pulsed mode is assumed, even if PLS is set to one. Additional information about strobe B can be found in 7.3.3 RIW (STRB) Pin.

EGA - Edge Select for Strobe A

This control bit selects which polarity edge will be recognized at the STRA input pin.

When EGA is zero, falling edges are detected and rising edges are ignored. When EGA is one, only rising edges are recognized at the STRA pin. When the three-state variation of the full-output handshake mode is being used, EGA also specifies the level on STRA that will cause port C output buffers to be enabled. The output enable for port C pins is an active-high internal signal, which is the exclusive OR of EGA with the level at the STRA pin. Thus, the trailing edge of the enable signal on the STRA pin will be the selected active edge used by the handshake sequence.

INVB - Invert Strobe B

The STRB signal is developed in an SIR flip-flop in the STRB pin logic. The INVB control bit selects either the Q or Q output of this flip-flop to be coupled out of the STRB pin.

If INVB is zero, the Q of this latch is coupled out of the STRB pin, and STRB signals are active low. If INVB is one, the Q of this latch is used, and STRB signals are active high. Changes to INVB do not affect the state of the internal SIR flip-flop.

7.4.5 Nonhandshake Uses of STRA and STRB Pins

When not being used for handshake functions, the STRA pin can be used as a general-purpose edge-detection interrupt source, which is fairly common use for the STRA pin.

The STAF is set each time a selected edge is recognized. The STAI control bit allows strobe A edges to force a maskable interrupt to the IRQ vector. The EGA control bit allows the user to select either rising edges or falling edges as the triggering edge for the strobe A input.

Though not a very common practice, the STRB pin can be used as an extra static output.

When full-input handshake mode is selected, STRB remains at its inactive level until the PORTCL register is read. If PORTCL is never read, STRB stays at its inactive level indefinitely.

The INVB control bit allows the user to switch the inactive level from one to zero by writing to the PIOC register. In this scheme, it is important never to read the PORTCL register • because this would cause STRB to automatically go to its active level. Other similar schemes may be developed to meet specific application needs.

Usually when the STRA and STRB pins are being used for non handshake functions, the handshake I/O subsystem would be configured for full-input handshake mode because the other two modes result in interactions between the strobe pins and the port Band C pins.

If simple strobe mode is selected, any write to port B will generate a pulse on the STRB pin. If full-output handshake is selected, each time the STRA pin goes to its selected active level, all port C pins are forced to be outputs (even if the DDRC bits indicate they should be inputs). These interactions are a normal consequence of the handshake I/O functions but could interfere with non handshake use of the STRA and STRB pins. For this reason, users are encouraged to study the operation of the handshake I/O subsystem carefully if they plan to use STRA and STRB for nonhandshake functions.

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