Timing Sources
• Use 625KC oscillator in 7631 or 625KC clock track signal from selected 1301 at 1.6 JLS rate.
• Oscillator or clock signal develops selected phase signal.
• Selected phase drives the delay line pulse generator.
• Delay line pulse generator drives all timing circuits in 7631.
Two signal sources are used for 7631 timing. A 625 KC
oscillator is used for control, sense, and prepare to read-write cycle timing, and the 1301 clock track signal is used for read and write timing. Either selected timing
source is applied to the delay line pulse generator input via the selected phase line when delay line pulse generator timing is needed (Figure 29). The delay line pulse generator develops one complete cycle of output
~ ,1.6 I~
I' I
__ 1.8 1 __ 1 1 1 I
1 1 I
~
-
OSC ~---~Oscillator Gated
~C=a~nt~ra~I ________ ~~
Sense
Prepare to Rd or Write '
-~B=-S ____ -l~~ _ _ _ _ -l~ Start Phase Select Read Data
Hold Phase
' - - - '
-~ 1.6
1---~.81~1
I I I
-0JG-~R=ea=d ____ ~~~ _ _
~L---Write
Figure 29. Timing Scheme
Phase Detect
40.19 Phase 1 Phase 2 Phase 3 Phase 4
...---_-"---1---, Ph
1
Selected Phase ~--..., Delay ,....--- Bit, - - -Se~;:t Line Line Pulse f--- A f - - - Ring
_ Circuits Generator
r- (See Figures 31 and 33) 10.16-17-18
Selected Phase
From oscillator
(See Figure 36) 10.19-20
Run Bit Ring
~ 1.6 I~
1 I
1 1
.... 1.8 1-- I
1 I 1
I I 1
SLS
I 1 1__ 1.41~
I
From 1301 clock track
J-Ls
(See Figure 37)
50.04-07
Run Digit Ring
Note: All time is in microseconds
B7 ---;:- Digit
~ r--- Ring
(See Figure 41) 70.01-04
Functional Units 51
pulses for each selected phase input cycle. A second group of timing pulses, bit ring timings, are developed from one of the delay line pulse generator outputs. Fin-ally, digit ring timing is developed from one of the bit ring outputs (Figure 29).
Oscillator or clock track timing is used for the se-lected phase. Sese-lected phase is the input to the delay line pulse generator (Figure 30). The delay line pulse generator outputs are used to read and write data,
op-Phase Select Scheme
erate the shift register, and to step bit ring. When digit ring timing is needed, bit ring timing is used to ad-vance the digit ring. Digit ring timing is used to start all machine operations. Briefly, one complete cycle of the delay line pulse generator timing equals one bit time. One complete cycle of the bit ring equals one character time (depending on the machine bit mode, either seven or nine bit times); 13 bit ring cycles equal one complete digit ring cycle.
• Use 1301 clock track signal when reading or writing on disk.
• Clock track signal develops selected phase in phase select circuits.
• Selected phase drives delay line pulse generator.
• Delay line drives bit ring which controls read or write data flow.
• 7631 bit ring timing and read or write data flow must be synchronized.
The phase select circuits provide timing pulses to the delay line pulse generator input. These fundamental bit timing signals, derived from either the clock track or the oscillator, are gated via the selected phase line to the delay line pulse generator (Figure 30). The delay line pulse generator outputs sample 1301 read data at the output of data trigger A, operate the shift register, sample write data going from the 7631 to 1301, and provide a precise sample for compare circuit opera-tions.
One of the delay line pulse generator outputs is used to drive the bit ring. Bit ring outputs gate the output of data trigger B (read data) into the correct serial reg-ister storage position; this allows each read character to be correctly assembled before transferring the
char-Read Mode
acter to the system. Because the clock track signal is the timing source that advances the bit ring when reading, the bit ring outputs hold a critical time rela-tionship to the read data bits; therefore, the clock track and read data must be synchronized. Loss of synchro-nization could cause the read data bits to be stored in the wrong serial register storage positions and cause data errors.
Read data and clock track signals require synchro-nization because the clock track and data heads are mounted on the ends of non-stable arms subject to vi-bration. The phase select circuits synchronize the read and clock track signals for reliable read operation. The phase select circuits have two different modes of oper-ation: read mode and hold phase.
• 1301 clock signal is divided into four 400 nanosecond phases.
• When reading data,data bit S of every character selects a clock phase.
• The selected phase provides timing for that character in step with read data.
• Two phase select circuits (A and B) are used alternately to allow an earlier phase to be selected when reading, if necessary.
• Hold phase is used to operate phase select circuit when writing or reading and valid read data is not available.
• Hold phase selects any phase and holds it until hold phase is reset.
Read and clock signal synchronization occurs when bit-sync is read from the data track. (Bit-sync is not part of the system write data, but is generated and
written by the 7631 as the first bit of each character.) Bit-sync is the first bit of each read character; bit-sync is compared with the four 1301 clock phases to select
Write Bus (7000)
1410 Read-Write Bus (Model 3) Read Bus (7000)
I/O
Reg
10.01-.03
1410 Read-Write Bus (Models 1 and 5) Not Compare Cycle
Compare Write
Write AGC Write Format
Not Compare Address
Clock Trigger
FMTWr l's Tgr
T
80.06.1
Figure 30. Data Flow Diagram
1410 Operation Code Bus File Start Gate Control
10.04-.10
Read Data
7000 Control
Comp Ckts
10.14
Shift Register 30.01-.06
Data Trigger B
T
R 10.15
Storage Bus
Acc MOD
Compare Fail Tgr
T
50.30 Reg
20.02
Read
Check Char Gate Data Trigger A
T
1600 ~~~---10.19-.20
Run Digit Trigger
Track
TO
Head
Seek
Control
Write
Phase Selection
Circuits
10.17-.18
Digit Ring
70.01-.03 Reg
Compare Address
Random
Rec Reg
To 1301 Access Reg
To 1301 Access Reg
To 1301 Acc/Mod Select
Write Data to 1301
Write or Hold Phase
Read Gate Raw Read Data (1301) Read-Write 4 Phase of 1301
Sense
the comparing phase. The comparing phase, selected phase in ALD terms, is the delay line pulse generator input, and the delay line pulse generator and the bit ring outputs are synchronous with read data.
Each bit-sync is used to select the phase for the fol-lowing read data bits to insure read synchronization.
The phase select circuits are designed to compare and select a phase for every character read; however, it is improbable that head vibration and disk speed varia-tions could cause a new phase selection more often than once every 60 characters. Because bit-sync is only needed for timing purposes and it is not part of system write data, bit-sync is never transferred to the system with a read data character.
Read Phase Select Operation
When reading data, the phase select circuits provide a selected phase input to the delay line pulse generator;
the resultant delay line pulse generator outputs are used to sample data, operate the shift register, and drive the bit ring. Two identical phase selectors, phase selector A and B, are alternately used to select the delay line pulse generator input. Four phase selector gates control clock phase outputs 1 through 4 for each phase selector. The output gates are labeled 4>1, 4>2, 4>3 and 4>4 in Figure 31. The input clock phases are sup-plied by the phase detector (Figures 29 and 31). The phase detector divides each 1.6 microsecond clock track signal into four phases; each phase is 400 nano-seconds in duration (Figure 32). The 7631 must select one of the phases for each character read.
Phase selectors A and B are identical. (The follow-ing description refers to phase selector B shown on the lower half of Figure 31.) The output gates of phase se-lector B each have a different phase input; the output gates are controlled by the B select odd and B select even triggers. The B select odd and even triggers are set and reset with same four phase signals that are ap-plied to the output gates. When the B odd and even triggers are continuously set and reset, a selected phase output cannot be obtained from phase selector B be-cause the output gate conditioning signals cannot AND
with the input phase signals. For example, if phase two (4)2) is the required selected phase, two simulta-neous conditions must occur to gate phase two (4)2).
1. The B phase select odd trigger must be reset.
2. The B phase select even trigger must be reset.
If these two conditions remain unchanged, phase two (4)2) is gated to the delay line pulse generator via the are the inverse of the conditions needed to gate phase two. (See the B selector phase two (4)2) output gate shown in Figure 31.) This difference between phase timing and phase gating never changes; therefore, when the input gates are conditioned, the phase selec-tor cannot supply a selected phase output.
When phase one (4)1) is available, output phase gate 4>3 is conditioned; similarly, when phase two is avail-able, output phase gate 4>4 is conditioned (Figure 31).
The two-phase difference between input and output gating prevents a phase selection when phase select trigger B output conditions the input phase gates.
The conditioning signal must be removed from the input gates to stop the select odd and even triggers;
stopping the select odd and even triggers gates one of the four phase signals to the selected phase line. (Fig-ure 34 shows the condition of the select odd and even triggers required to gate each phase.) When set, phase select B trigger blocks the B selector input gates; there-fore, phase select B trigger stops the B select odd and even triggers and permits output phase gating (a phase selection).
If the set pulse timing to the phase select B trigger is controlled, the selected phase can be controlled. For digit timing is needed) are generated. Raw read signals from the 1301 are then sampled (converted to pulses) to determine if the data bits are ones or zeros.
To select the correct read phase signal, bit-sync (the first bit read), BS from the bit ring, and the binary trig-ger output AND; phase select B trigger sets (Figure 33).
Phase select B trigger blocks the B selector input gates;
the time the bit-sync arrives in relation to one of the four phases determines when the odd and even triggers stop. For example, if bit-sync is coincident with phase three, phase one is the selected phase. (Figure 34 shows the coincidence of bit-sync with each phase and the re-sultant selected phase output.) Selected phase one (4)1) drives the delay line pulse generator to sample data and drive the bit ring.
When the bit ring steps from B7 (the last output pulse) it returns to BS, the starting output. While read-ing the first character and steppread-ing the bit rread-ing, the binary trigger is flipped with the B4 bit ring output.
The binary trigger conditions the phase select B trig-ger reset and the phase select A trigtrig-ger set; these
con-A 9S1 Output Gates A Odd
Read Data T
Odd A Even
Sel New 0
R T
1200 ns Odd A <j53
R A Odd
A Even Even
9S2
T A Odd
02 Even A A Even
9S4 Selected
01 AO Phase 0
Hold 0 SZl4 (1)
Phase 02 0"
'<
B4 BT Detect 9S3
r-~ 5· (1)
)61
Reset Off B Odd
01 Odd BEen
Odd B 03
Read Data Sel New 0
1200 ns
Even ~~----~ ____ ~~ . . . . ~ ______ _ Odd
Clock
---~~~---~~~---______
~r! ~Figure 31. Phase Selector Circuits-Simplified
1301 Clock Track Signals
Phase 1
Phase 2
Phase 3
Phase 4
~ n
n n
* All timing is in microseconds.
Figure 32. Phase Detector Inputs and Outputs
n
n
ditions gate the next bit sync to set phase select A trig-ger. When phase select A trigger is set, it provides a selected phase for the second character read from the 130l. (Phase selector A operates in the same manner as phase selector B for the next character cycle.) Phase se-lect B trigger is reset with 1200 delayed (from the delay line pulse generator), gated with BS from the bit ring, and phase selector B stops operation. (In Figure 35, lines 1 through 13 show the read data timing se-quence, and lines 10 and 11 show how read timing causes phase select A and B triggers to alternately set and reset.) Phase select A trigger is set while the first address character is read, then phase control is switched to phase select trigger B for the second address char-acter. The phase select triggers alternate the phase se-lectors until the read data is processed.
n
rL
Phase Detector Input
Phase Detector Outputs
Figure 35, line 7, shows when the read gate is on;
the timing circuits operate in read mode when the read gate is on. Note that the D7 (line 13) digit ring output has greater duration than the D6 output. The gap pre-ceding the last address data character is always written without a bit-sync, so that there are no read data bits to select phase. Because both phase select A and B triggers remain reset in the data gap, the read timing is suspended and, in this case, D7 is available for an ex-tended time interval. Whenever both phase select A and B triggers are reset and the read gate is set, the phase selectors are conditioned to detect missing sync.
(See the AND circuit between phase selectors A and B on Figure 33.) The missing sync detection AND circuit output is used to prepare the 7631 to process the check characters read immediately after the last address or record data character.
BS r
r--t-Figure 33. Phase Selector Circuits
Phase Selector A