The on-chip FLASH memory of the STM32 is arranged in three main regions. First, there is the main FLASH memory designed to hold program instructions. This memory is 64 bits wide to provide efficient memory access with the prefetch buffer. For flash program and erase operations this memory is divided into 4K pages. This memory has a WRITE endurance of 10000 cycles and data retention of 30 years at 85 degrees C. Most microcontroller FLASH memory data retention is rated at 25 degrees C, so the STM32 has an exceptional FLASH memory. Aside from the main program memory, there are two smaller memory regions: the big information block and the small information block. The big information block is a further 2k of FLASH memory holding a factory FPEC is also used to program the option bytes in the small information block.
8.2 Erase And Write Operations
After reset, the FPEC registers are protected and must be unlocked by writing a special sequence to the key register. To unlock the FPEC you must write 0x45670123, followed by 0xCDEF89AB. If there is a mistake in this sequence, the FPEC will stay locked until the next reset. Once the FPEC has been unlocked, it is possible to erase and WRITE operations on the main FLASH memory. Within the main FLASH memory block it is possible to perform a mass erase or an erase of a selected 4k page. A mass erase is done by simply setting the mass erase and start bits in the control register. When the busy bit in the same register is reset, each location in the main FLASH memory will be reset to 0xFFFF. A page erase is equally easy to perform. First, you must program the start address of a FLASH page into the Address register, then set the page erase and start bits in the control register. Again, when the busy bit is clear, the page will be erased. New data can be written to a FLASH memory cell only after it has been erased. A WRITE operation is performed by setting the program bit in the control register and then performing a half-word write to the desired location. If the FLASH location is erased and not write protected, the FPEC will program the new value into the FLASH memory cell.
8.3 Option Bytes
The small information block contains eight user-configurable option bytes. Four of these bytes are used to define write protection on the main FLASH memory. The fifth is used to set read protection which prevents access to regions of memory when the chip is in debug mode. A sixth byte is used to configure low power and reset operation. The final two bytes are simple FLASH memory cells that are available for user-defined options. Before the Option bytes can be written to, the FPEC must be unlocked as described above. Then the Option bytes must
The FPEC module is used to allow in- application programming of the FLASH memory. The FLASH memory can also be read-protected from debug tools and write-protected.
and erase procedure to the main FLASH memory. The small information block is erased by setting the OPTER bit in the control register and then the STRT bit. Once the BSY bit is reset, the small information block is erased. To program an Option byte, set the OPTPG bit in the FLASH control register and perform a half-word write to the Option byte. Each Option byte is stored as a word. The Option byte is stored in the lower byte of the half-word and its complemented value is stored in the upper half-half-word. You must write a correct value in the lower half-word and the FPEC will automatically calculate the complemented value.
8.3.1 Write Protection
When it is set, each bit in the write protection option bytes enables protection over a given FLASH page. Write protection can be disabled by an erase of the small information block.
8.3.2 Read Protection
When the read protection is set, all read accesses to the FLASH memory are disabled when the device enters debug mode. Access to the SRAM is still possible and code may be downloaded and executed in this region. So it is possible to disable the read protection by running a program out of SRAM. However, when read protection is disabled a mass erase of the internal FLASH is also performed, to ensure protection from software piracy. When read protection is enabled, the FLASH memory is also write protected to prevent a malicious program from being inserted into the memory region containing the vector table. The STM FLASH memory is protected if the read protection byte and its complement are set to 0xFF. The memory can be unprotected by writing 0xFA and its complement as a half-word to the read protection Option byte.
8.3.3 Configuration Byte
The configuration Option byte contains three active bits. Two of these bits govern how the STM32 enters Standby and Stop modes. Either mode can be configured to generate a reset on entry. This will configure the digital IO pins as inputs, reducing the overall power consumption of the STM32. The PLL and external oscillator will also be disabled and the chip will revert to using the internal high speed RC oscillator as the main system clock. The final bit in the configuration Option byte configures the activation of the independent watchdog. This watchdog has a hardware watchdog mode where it will start immediately after a processor reset, or software watchdog where it must be started under software control.