Exception Recognition and Priorities

Exceptions are roughly prioritized by exception class, as follows:

1. N onmaskable, asynchronous exceptions have priority over all other exceptions-system reset and machine check exceptions (although the machine check exception condition can be disabled so the condition causes the processor to go directly into the checkstop state). These exceptions cannot be delayed and do not wait for completion of any precise exception handling.

2. Synchronous, precise exceptions are caused by instructions and are taken in strict program order.

3. Imprecise exceptions (imprecise mode floating-point enabled exceptions) are caused by instructions and they are delayed until higher priority exceptions are taken. Note that the 750 does not implement an exception of this type.

4. Maskable asynchronous exceptions (external, decrementer, thermal management, system management, performance monitor, and interrupt exceptions) are delayed until higher priority exceptions are taken.

The following list of exception categories describes how the 750 handles exceptions up to the point of signaling the appropriate interrupt to occur. Note that a recoverable state is reached if the completed store queue is empty (drained, not canceled) and any instruction that is next in program order and has been signaled to complete has completed. If MSR[RI] = 0, the 750 is in a nonrecoverable state. Also, instruction completion is defined as updating all architectural registers associated with that instruction, and then removing that instruction from the completion buffer.

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• Exceptions caused by asynchronous events (interrupts). These exceptions are further distinguished by whether they are maskable and recoverable.

- Asynchronous, nonmaskable, nonrecoverable

System reset for assertion of HRESET -Has highest priority and is taken immediately regardless of other pending exceptions or recoverability. (Includes power-on reset)

IBM PowerPC 740 I PowerPC 750 RISC Microprocessor User's Manual

- Asynchronous, maskable, nonrecoverable

Machine check exception-Has priority over any other pending exception except system reset for assertion of HRESET. Taken immediately regardless of recoverability.

- Asynchronous, nonmaskable, recoverable

System reset for SRESET -Has priority over any other pending exception except system reset for HRESET (or power-on reset), or machine check. Taken immediately when a recoverable state is reached.

- Asynchronous, maskable, recoverable

System management, performance monitor, thermal management, external, and decrementer interrupts-Before handling this type of exception, the next instruction in program order must complete. If that instruction causes another type of exception, that exception is taken and the asynchronous, maskable recoverable exception remains pending, until the instruction completes. Further instruction completion is halted. The asynchronous, maskable recoverable exception is taken when a recoverable state is reached.

• Instruction-related exceptions. These exceptions are further organized into the point in instruction processing in which they generate an exception.

- Instruction fetch

lSI exceptions-Once this type of exception is detected, dispatching stops and the current instruction stream is allowed to drain out of the machine. If completing any of the instructions in this stream causes an exception, that exception is taken and the instruction fetch exception is discarded (but may be encountered again when instruction processing resumes). Otherwise, once all pending instructions have executed and a recoverable state is reached, the lSI exception is taken.

- Instruction dispatch/execution

Program, DSI, alignment, floating-point unavailable, system call, and instruction address breakpoint-This type of exception is determined during dispatch or execution of an instruction. The exception remains pending until all instructions before the exception-causing instruction in program order complete. The exception is then taken without completing the exception-causing instruction. If completing these previous instructions causes an exception, that exception takes priority over the pending instruction dispatch/execution exception, which is then discarded (but may be encountered again when instruction processing resumes).

- Post-instruction execution

Trace-Trace exceptions are generated following execution and completion of an instruction while trace mode is enabled. If executing the instruction produces conditions for another type of exception, that exception is taken and the post-instruction exception is forgotten for that post-instruction.

Note that these exception classifications correspond to how exceptions are prioritized, as described in Table 4-3.

Table 4-3. PowerPC 750 Exception Priorities

Priority Exception Cause

Asynchronous Exceptions (Interrupts)

0 System reset Power on reset, assertion of HRESET and TRST (hard reset)

1 Machine check Any enabled machine check condition (L 1 address or data parity error, L2 data parity error, assertion of TEA or MCP)

2 System reset Assertion of SRESET (soft reset) 3 System management Assertion of SMI

4 External interrupt Assertion of I NT

5 Performance monitor Any programmer-specified performance monitor condition 6 Oecrementer Oecrementer passes through zero

7 Thermal management Any programmer-specified thermal management condition Instruction Fetch Exceptions

0 lSI Any lSI exception condition

Instruction Dispatch/Execution Exceptions 0 Instruction address Any instruction address breakpoint exception condition

breakpoint

1 Program Occurrence of an illegal instruction, privileged instruction, or trap exception condition. Note that floating-point enabled program exceptions have lower priority.

2 System call System Call (sc) instruction

3 Floating-point Any floating-point unavailable exception condition unavailable

4 Program A floating-point enabled exception condition (lowest-priority program exception) 5 OSI OSI exception due to eciwx, ecowx with EAR[E] = 0 (OSISR[11 D. Lower priority

OSI exception conditions are shown below.

6 Alignment Any alignment exception condition, prioritized as follows:

1 Floating-point access not word-aligned 2 Imw, stmw, Iwarx, stwcx. not word-aligned 3 eciwx or ecowx not word-aligned 4 Multiple or string access with MSR[LE] set

5 dcbz to write-through or cache-inhibited page or cache is disabled

7 OSI BAT page protection violation

8 OSI Any access except cache operations to a segment where SR[T] = 1 (OSISR[5D or an access crosses from a T = 0 segment to one where T = 1 (OSISR[5D

9 OSI TLB page protection violation

10 OSI OABR address match

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Table 4-3. PowerPC 750 Exception Priorities (Continued)

Priority

I

I

Post-Instruction Execution Exceptions 11

I

I

System reset and machine check exceptions may occur at any time and are not delayed even if an exception is being handled. As a result, state information for an interrupted exception may be lost; therefore, these exceptions are typically nonrecoverable. An exception may not be taken immediately when it is recognized.