The Direct Memory Access Request I .. O ... M.,..A .... R ... EO"") pulse Iwhen enabled) is associated with output or input transfers to keep the initial and final output latches full or initial and final input latches empty, respectively. Fig\Jres 13 and 14 show all the possible paths in generating DMA requests.
OMAREQ is generated on the bus side of the MC68230 by the synchronized' Chip Select. If the conditions of Figures
Om Regilter Data Regilter
3 FIL,D.B IOLlFDL, D.B., Note 1 WITH OUTPUT TRANSFERS
Data In Output Latches
No DMA Request Peripheral Accepts Data
~CByte~/
WITH INPUT TRANSFERSData In Input Latches
~COByte0~
Peripheral PrOl/Ides Data No DMA Request
~ t
OMA A> c' B'''::><' A,,,
Peripheral Provides Data DMA Request
~ ,
No DMA Request Bus Read
~C2BYte~/
'Synchronized means that the Input signal has been seen by the PIIT on the appropriate edge of the clock Irlslng edge for H11H31 and tailing edge for CSI IRefer to the BUS INTERFACE CONNECTION section for the exception concernlnq ~11f a bus access lassertlon of CSI and a port access {assertion of H11H311 occur at the same time, ~ will be recognized Without any delay. H11H31 will be recognized one clock cycle later
TIMER
The MC68230 timer can provide several facilities needed by MC68000 operating systems. It can generate periodic in-terrupts, a square wave, or a single interrupt after a pro-grammed time period. Also, it can be used for elapsed time measurement or as a device watchdog. This section describes the programmable options available, capabilities, and restrictions that apply to the timer. counter signals the occurrence of an event primarily through zero detection. IA zero IS when the counter of the 24-bit progr,lmmable The timer IS fully configured and controlled hy programming the8-blt Timer Control Register It controls' 111 the chOice between the Port C operation and the timer llperatlon of three timer pins, 121 whether the counter IS load-l'd frpm·the Counter Preload Register or rolls over when zero detect IS reach, 131 the clock Input, (41 whether the prescaler
,S dsed, and 151 whether the timer IS enabled RUN I HALT DEFINITION
r
he overall operation of the timer IS described In terms of til(' rurl 01 halt states The control of the current state is dptelmlned by programming the Timer Control Register Wh('1l HI til(' halt stdte, all of the follOWing occur1 The pnor contents of .the counter IS not altered and IS reliably readable via the Count Registers
2 The prescaler IS forced to $1 F whether or not It IS used.
ThiS section prOVides a set of rules that allow easy applica-tion of the timer
1 Refer to the Run/Halt Definition above
2 When the
R'fS'fi'
Pin IS asserted, all bits of the Timer Control Register go to 0, configuring the dual function pins as Port C Inputs.3 The contents of the Counter Preload Registers and counter are not affected by the RESET pin.
4 The Count Registers prOVide a direct read data path from each portion of the 24-blt counter, but data Writ-ten to their addresses IS Ignored. (ThiS results In a nor· any timer operation. No protection mechanisms are provided against ill-timed writes.
6. The input frequency to the 24·bit counter from the TIN pin or prescaler output, must be between
°
and the in-put frequency at ClK pin divided by ;32 regardless of the configuration chosen.7. For configurations in which the prescaler is used (With the CLK pin or TIN pin as an input I , the contents of transferred to the counter on the first asserted edge of the TIN Input after entering the run state On subse-Quent asserted edges the counter decrements or IS loaded from the Counter Preload Registers.
9. The lowest value allowed In the Counter Prel03d Register for use With the counter IS SOOOOOI
TIMER INTERRUPT ACKNOWLEDGE CYCLES
Several conditions may be present when the timer Inter-rupt acknowledge pin ITIACKI is asserted. These conditions affect the Pill's response and the termination of the bus cy-cle. (See Table 9.1
TABLE 9 - RESPONSE TO TIMER INTERRUPT ACKNOWLEDGE PC31T0UT Function Response to Assened TIACK PC3 Port C Pill Nu rtlS~)()ll~f' Interrupt Requ"st 01 AC" As,,,-I"ll
PROGRAMMER'S MODEL
The Internal acceSSible register organization IS represented In Table 10. Address space Within the address map IS re-served for future expansion. Throughout the PliT data sheet the following conventions are maintained.
1. A read from a reserved location In the map results In a
3. Bits that are u'hused in the chosen mode/submode but are used in others, are denoted by "X", and are readable and writeable. Their content, however, is Ig-nored in the chosen mode/submode
4. All registers are addressable as 8-bit Quantities To facilitate operation with the MOVEP inStruction and the DMAC, addresses are ordered such that certain sets of registers may also be accessed as words 12 bytes I or long words (4 bytes)
MOTOROLA Semiconductor Products Inc.
MC68230LSeMC68230L 10
TABLE 10 - PitT REGISTER ADDRESSING ASSIGNMENTS
Register Affected
Register SeKt BAs Accessible by
5 4 3 2 1 Reset
The Port General Control Register controls many of the func-tions that are common to the overall operation of the ports, The PGCR IS composed of three malar fields: bits 7 and 6 deftne the operational mode of Ports A and B and affect operation of the handshake pms and status bits; bits 5 and 4 allow a software controlled disabling of particular hardware associated With the handshake pins of each port; and bits 3-0 define the sense of the handshake pins The PGCR IS always readable and wmeable,
PGCR
7 6 Port Mode Control
o
0 Mode 0 (UnldlreClional 8-Blt Modelo
1 Mode 1 (Unldtrectlonal 16-Blt Modelo
Mode 2 (Bidirectional 8-Blt Model Mode 3 (Bidirectional 16-Blt Model PGCR respective operation! slo
The associated pin is at the high-voltage level when negated and at the low-voltage level when asserted, The associated pin IS at the low-voltage level when negated and at the high-voltage level when assertedMC68230LS·MC68230L 10 The Port Service Request Register controls other functions that are common to the overall operation to the ports. It is composed of four major fields: bit 7 is unused and is always read as 0; bits 6 and 5 define whether interrupt or DMA re-quests are generated from activity on the Hl and H3 hand-shake PinS; bits 4 and 3 determine whether two dual function pins operate as Port C or port Interrupt request I -acknowledge pins; and bits 2, 1, and 0 control the priority among all port Interrupt sources. Since bits 2, 1, and 0 affect Interrupt operation, It IS recommended that they be changed only when the affected Interrupt(s) is lare) disabled or known to remain inactive. The PSRR IS always readable and and IS assoclateu With double-buffered transfers con-trolled by Hl Hl IS removed from the PIIT's Interrupt structure, and thus, does not cause Interrupt requests tll be generated To obtain DMAREO pulses, Port A Centrol Register bit 1 (HI SVCRO Enable) must bea 1 lIThe PC41 DMAR EO Pin carries the DMAREO function
and IS assOCiated with double-buffered transfers con-trolled by H3. H3 IS removed from the PIIT's Interrupt structure, and thUS, does not cause Interrupt requests
10 be generated To obtain DMAREO pulses, Port B
Bits 2, 1, and 0 determine port interrupt priOflty The priority IS Shown In descending order left to fight.
PSRR Port Interrupt Priority Control 2 1
Q.
Highest ... Lowest Data Direction Register determines the direction and buffer-Ing characteristiCS of each of the Port fj.. pins. One bit In the PADDR is aSSigned to each pin. A 0 indicates that the pin IS used as an input. while a 1 indicates It IS used as an output The PADDR is always readable and wflteable. ThiS register ISIgnored in Mode 3. _ _ Data Direction Register speCifies whether each dual-function pin that is chosen for Port C operation IS an Input 10) or an output III pin The PCDDR, along With bits that determine the respective pin's function. also speCify the exact hardware to be accessed at the Port C Data Register address. I See the Port C Data Register descnption for more details) The PCDDR IS an a-bit register that IS readable and wflteable at all times. Its operation IS Independent of the chosen PI/ T mode
These bits are cleared to 0 when the RESET Pin IS asserted.
Port Interrupt Vector Register (PIVR)
-o
Interrupt Vector Number
*'
The Port Interrupt Vector Register contains the upper order SIX bits of the four port interrupt vectors The contents of this register may be read two ways: by an ordinary read cy-cle, or by a port interrupt acknowledge bus cycle. The exact data read depends on how the cycle was initiated and other factors. Behavior dunng a port Interrupt acknowledge cycle IS summarized above in Table 3.