Control Ctrl Control Enable The Timer Control Register ITCRI determines all operations of the timer. Bits 7-5 configure the PC3ITOUT and PC71TIACK pins for Port C. square wave. vectored Inter·
rupt, or autovectored Inter.rupt operation, bit 4 speCifies wt1('thl'r the counter reCPIVl', Odtd from thp Counter Preload Rf'ljlster or contll1lJt!s counting wtH'n lero detect IS reached, bit 3 IS unused and IS read as 0, bits 2 and 1 configure the dual· function pin PC71TIACK carries the TlACK function, however, since Interrupt request is negated. the PIIT produces no response. I.e, no output. The timer interrupt is enabled; thUS. the pin is low when the timer ZOS status bit is 1. The dual function pin PC7/TIACK carries ·the TIACK func-tion and is used as a timer interrupt acknowledge input. Refer to the Timer Interrupt Acknowledge Cycle section for details. This combination and the 100 state abov~ support vectored timer interrupts.
TCR
o
The dual-function pin PC3ITOUT carries the TOUT function. In the run or halt state it is used as a timer interrupt request output. The timer interrupt is disabled; thus, the pin is always three·stated. The dual· function Pin PC71TIACK carnes the PC7 func-tion.The dual-function pin PC3ITOUT carries the TOUT function and IS used as a timer interrupt request output. The timer Interrupt IS enabled; thus. the pin is low when the timer ZOS status bit IS 1. The dual-function pin PC7 ITIACK carnes the PC7 dual-function and autovectored interrupts are supported
4 Zero Detect Control Counter Preload Registers when the prescaler rolls over from $00 to $1 F The Timer Enable bJ! determines Counter Preload Registers when the prescaler rolls over from $00 to $1 F The timer IS III the run st,ltl' when the Timer Enable bit IS 1 and the TIN pin IS high otherWise the timer IS In the halt state
o
The PC2ITIN pin serves as a timer Input and the prescaler IS used. The prescaler IS decremented follow·Ing the rising tranSition of the TIN pin after syncing With the internal clock. The 24-bit counter IS decremented or loaded from the counter preload registers when the prescaler rolls over from $00 to $1 F The Timer Enable bit determines whether the timer IS in the run or halt state.
The PC2ITIN pin serves as a timer Input and the prescaler IS unused. The 24-blt counter IS decremented or loaded from the Counter Preload Registers follow Ing the rising edge of the TIN pin after syncing With the internal clock. The Timer Enable bit determines whether the timer IS In the run or halt state
MOTOROLA Semiconductor Products Inc.
MC68230LS-MC68230L 10
TCR
o
Timer Enableo
Disabled.1 Enabled.
Timer Interrupt Vector Register (TIVR) - The timer inter-rupt vector register contains the 8-bit vector supplied when the timer interrupt acknowledge pin TlACK is asserted. The register is readable and wnteable at all times, and the same value is always obtained from a normal read cycle and a timer Interrupt acknowledge bus cycle (TIACK). When the RESET pin is asserted the value of $OF is automatically loaded into the register Refer to Timer Interrupt Acknowledge Cycle section for more details. counter, which may be occunng simultaneously
To Insure proper operation of the Pill Timer, a value of group may be accessed with the MOVEP. L or the MOVEP W instructions. The address one less than the address of CNTR H IS the null register, and IS reserved 5>0 that zeros are read In the upper 8 bits of the destination data register when a MOVEP. L IS used. Data wntten to thiS address IS Ignored
Timer Status Register (TSR)
-I. 1 : 1 : 1 : 1 : 1 : 1 ·1':5 I
The Timer Status Register contains one bit from which the zero detect status can be determined The lDS status b,r Iblt 01 IS an edge· sensitive flip flop Ihat IS set to 1 when Ihe 24 bit zero detect condition
Bits 7·1 are unused and are read as 0
TIMER APPLICATIONS SUMMARY
ThiS section outlones programming of Ihe l'fTH" C()f\tr()1 Reqlster for several tYPical examples
Periodic Interrupt Generator
I
tiI
':J ~ .\I
The processor loads the Counter Preloild Registers clf\[j Timer Control Register, and then eflilbles the time' Whf!"
MC68230L8·MC6823(JL 10
FIGURE 15 - PERIODIC INTERRUPT GENERATOR
,.. H u l l
Square Wave Generator
I
tiI
" -lI
In thiS configuration the trmer generates 'an Interrupt after a programmed time period has expired. The TOUT prn IS connected to ticr system's rnterrupt request Circuitry and the TIACK pin may be an Interrupt acknowledge Inpu! to the timer The TIN pin may be used as a clock Input
Thrs configuratron IS slmrlar to the perrodlc -Interrupt generator except that the Zero Detect Control bit IS set ThiS routine Accurate knowledge of the Interrupt latencv may be useful In some applications (see Figure 171
• Analoq rp-present~tlon ot counter value
Elapsed Time Measurement
Elapsed time measurement takes several forms, two ,lit'
Thrs configuration allows time Interval measurement bv software No timer pinS are used
The processOi ,.Ioads tile COUllter Preload Rey,stprs tgenerally wrth all Is) and Tlmel ContrOl Rpqlster, alld tl)!'"
enables the tllner The counter decrements until the endillq event takes place When It IS desiled to read the tlnl!' 111\('1 val, the processor must halt tne timer, then read the COUll tel For applications In which the Interval could have exceeded that programmable In thiS timer, Interrupts can be counted to prOVide the eqLJlvalent of additional timer bits At the end, the timer can be halted and read (see Frgure 181
MOTOROLA Semiconductor Products Inc.
MC68230U3-MC682:30L 1()
FIGURE 18 - ELAPSED TIME MEASUREMENT
,... H'H' _,
External Clock
Tills "(lIlf"l'"cltllHl allows m'~clsurpmpl1t (coul1tll1<JI 01 th"
""nlh!', 01 II1P'lt ,Hlise's l1CcurllnrJ III iln IIltelval 111 which IIw CO'Jllt'~1 IS elldllied TI1£' TIN IIlpUt pill PI()VIOf'S tile IIllHlt IHlisps Gf'I1P'cilly th', TOU T ilnd TIACK PillS ilre not "SPO
1111" conlilllH:1I1011 IS IOl'l1tIG]: to the ElilPSPO TII11(' M"ds""''''''111 SYSIPlli Clock Cllllilll'"cltI(1I1 "xcept thill th"
T IN pill" Ih,'dl,' PI"VI(It' Ill(' 1111",1 Ilt'q"t'IICY II Cdll he "Oil
fll'I'lt'd III d <-;lrll~\lt, ()~('ill,ltl'r. cll1(i lilt, S(H1H~ rlH~tll()rl~; cOld<i tH~
,,:;cd AII.'''',]I,'I,;, 11"""1,, Ill: q.ll"t! ult dllli ,m t'X1erlldlly d"d Ihe n"mhel 01 c,clps occurllng while In the rlln state call be COUll led However, nlllOinlllm pulse Width 111gh dnd low
~pPl'I!Il'c1tl()rh rnust hfl rllP!
Device Watchdog r('milill npgated It Zero Detect IS reached while the TIN Input IS still dsserlpd thp ZDS status b,t IS set and the TOUT output
BUS INTERFACE CONNECTION
The Pill has an asynchronous bus Illterface, pnmarliy deSigned for use With the MC68000 microprocessor With care, however, It can be connected to synchronous microprocessor buses ThiS section completely descnbes IhfJ PIIT's bus Interface, and IS II1tended for the asynchronous bus deSigner unless otherWise mpntloned
In an asynchronous system the PII T ClK may operate at d
Significantly different frequency, either higher or lower, illa"
the bus master and other system components, as long as all bus speCifications are met The MC68230 ClK pili !las Ihp same SpeCdlcatlons a<; the MC68000 ClK, and must not he gated off at any time
The followll1g slgrodls generate nornlill read and wllte cycles to the PIIT CS (Chip Select), R/W IRead/Wntei RS1-RS5If,ve Register Select bitS), 00,071the8 bit bldller tlonal data busl, and OT ACK I Data Transfer Acknowledge l To generate II1lerrupt acknowledge cycles PC6!PIACK or PC71llACK IS used Instead of CS, and the Register Select pins are Ignored No combll1atlon of the followll1g pins may be asserted Simultaneously CS, PlACK, or TIACK READ CYCLES VIA CHIP SELECT
ThiS catagory Includes all register reads, t~xcert port or timer Interrupt acknowledge cycles When CS IS ilSSt'rtPli,' the Register Select and R I
IN
II1PUtS are latched Interrlalliv They must meet small setup and hold time requllements With respect to the asserted edge of CS (See the AC ElEC TRICAl CHARACTERISTICS table) The PIIT IS not pro, tected agall1st aborted Ishortened) bus cycles generated by an Address Error or Bus Error exception In which II IS addressedCertall1 operations tnggered by normal read lor wntei bus cycles are not complete Within the time allotted to the t,us cycle, One example IS transfers tolfrom the double-bulttlred latches that occur as a result of the bus cycle If the blls master's ClK IS Slgnd,cantly laster than the PI' T's the pOSSibility eXists that, followlI1g the bus cycle, C S can be
negated then re-asserted before completion of these internal operations In this situation the PlfT does not recognize the re-assertion of CS until these operations are complete. Only at that time does it begin the internal sequencing necessary to react to the asserted CS Since CS also controls the OT ACK response, this "bus cycle recovery time" can be related to the ClK edge on which OT ACK is asserted for that cycle The PlfT will recognize the subsequent assertion of Internal data bus of the PlfT IS continuously enabled for read transfers, the read access time Ito the data bus buffers) beginS when the Register Selects are stabilized Internally.
Also, when the PlfT is ready to begin a new bus cycle, the assertion of CS enables the date. bus buffers within a short propagation delay This does not contribute to the overall read access time unless CS IS asserted significantly after the Register Select and R
IW
Inputs are stabilized las may occur With synchronous bus microprocessors)In addition to Chip Select's previously mentioned duties, It controls the assertion of OT ACK and latching of read data at Select remains asserted Independent of other external condl-tillns acknowledge cycles, see Read Cycles via Interrupt t'dnowledge I
In asynchronous bus systems In which the PIIT's ClK dif-fers from that of the bus master, generally there IS no way to trailing (negated) edge of Chip Select to the negated edge of DT ACK. As system speeds increase this becomes more dif-ficult to meet with a simple pullup resistor tied to the DT ACK line. Therefore, the PlfT provides an internal active pullup device to reduce the rise time, and a level-sensitive Circuit that later turns this device off. DTACK is negated asyn-chronously as fast as pOSSible follOWing the rising edge of Chip Select. then three-stated to aVOid .lnterference With the next bus cycle.
The system designer must take care that OT ACK IS negated and three-stated qUickly enough after each bus cycle to avoid Interference with the next one. With the MC68000 thiS necessitates a relatively fast external path from the data strobe to CS going negated
WRITE CYCLES
In many ways write cycles are Similar to normal read cycles (see above) On wrtte cycles, data at the 00 07 pins must meet the same setup speCifications as the Register Selec1 and R/W lines. like these Signals, wrtte data IS latched Ofl the asserted edge of CS, and must meet small setup anel hold time requirements With respect to that edge The same bus cycle recovery conditions eXist as for normal read cycles No other differences eXIst.
READ CYCLES VIA INTERRUPT ACKNOWLEDGE SpeCial internal operations take place on PIIT Interrupt acknowledge cycles. The Port Interrupt Vector Register or the Timer Interrupt Vector Register are ImpliCitly addressed by the assertion of PC61 PlACK or PC71TIACK, respectively The Signals are first synchronized With the failing edge of the ClK One clock pertod after they are recognized the data bus buffers are enabled and the vector IS drtven onto the bus OT ACK IS asserted after another clock pellod to allow the vector some setup time p"or to OT ACK OTACK IS regated.
then three-stated as With normal read or wllte cycle, when PlACK or TIACK IS negated
MOTOROLA Semiconductor Products Inc.
MC68230LS-MC68230L 10
1---MILLIMETERS DIM MIN MAX
A 60.35 61.57 8 14.63 15.34 C 3.05 4.32 0 0.381 0.533 F 0.762 1.397 G 2.54 SSC J 0.203 0.330 K 2.54 4.19 L 1499 15.65
M 00 100
N 1.016 1.524
PACKAGE DIMENSIONS
o -- -
---INCHES MIN MAX 2.376 2.424 0.576 0.604 0.120 0.160 0.015 0.021 0.030 0.055 0.100 SSC 0.008 0.013 0.100 0.165 0.590 0616 00 100 0.040 0.060
]
---J
NOTES
8
L SUFFIX CERAMIC PACKAGE
CASE 740-02
1 DIMENSIONmlS DATUM 2. POSTIONAL TOLERANCE FOR LEADS
1.
ii! 02510010IlM'l{At3' 3OJ
IS SEATING PLANE.4 DIMENSION "L" TO CENTER OF LEADS WHEN FORMED PARALL~L DIMENSIONING AND TOLERANCING
PER ANSI Y145. 1973
Motorola reserves the right to make changes to any products herein to Improve reliability. tunctl'ln or design Motorola does not assume df·, liability arising out of the application or use of any prcxjuct or CirCuit described herein, neither does It convey any license under Its patent rights nor the fights of others