DIRECT MEMORY ACCESS

Direct memory access (DMA) allows data to be transferred between any F8 microprocessor system memory and an ex-ternal device, bypassing the 3850 CPU. Data is transferred in parallel with any CPU operations. DMA has been described, as a concept, in Sections 2.6.3 and 2.8.

One 3852 DMI device must be present in a microprocessor system that supports DMA. Up to four 3854 DMA devices may be present in the system; each 3854 DMA device provides one DMA channel.

8.4.1 When to Use DMA

DMA is used to transfer data into, or out of, a microprocessor system that has heavy 1/0 requirements. For example, using programmed 1/0, the theoretically maximum data transfer rate is implemented by the following instruction sequence for data input:

Scratch pad register 1 is assumed to hold the initial character count.

These four instructions execute in 9.5 instruction cycles, equal to 19 ps, using a 500 ns clock pulse. Assuming that external this maximum data transfer rate requires external logic that processes data at a rate of one byte every 1 9 J..Ls. Most ap-plications will not meet this requirement, usually because data transfer rates are set by logic considerations beyond the microprocessor system; that is, external logic determines data transfer rates, not the microprocessor system.

Suppose external logic is inputting data to the microprocessor system at some rate, which we will label R bytes/second.

The time that elapses between each byte transferred will be (l,OOO,OOO/R) J,ls. The local timer can be used to generate

EI ENABLE INTERRUPTS

POP RETURN

It will take approximately 38 J,lS for interrupt service routine ISRI to execute; this means that approximately 9.7 ms will be required to input 256 bytes of data. This 9.7 ms will be spread over whatever time interval the external device re-quires to transfer 256 bytes of data. But there are some problems associated with the method of inputting data:

1) Recall that there are certain privileged instructions which inhibit acknowledgement of an interrupt. It is quite feasible for a 2 to 4 J,lS delay to randomly get inserted between each execution of ISRI if, by chance, a privileged instruction is being executed at the instant the local timer times out. Over 256 bytes of data trans-fer, this means that it is feasible for a 500 J,ls slew to develop, which will result in the loss of a byte of data, if the data transfer rate exceeds 2,000 bytes/so 2) If the microprocessor is handling interrupts other

than the local timer, clearly other interrupts must be serviced by routines which are themselves interrupt-able, since one interrupt service routine blocking out ISRI for any significant period of time would almost certainly create irrecoverable timing errors.

3) Observe that ISRI uses the DCl register and uses one scratchpad register to store accumulator contents.

This means that the DCl register and th~ ~cratchpad

register cannot be used by any other program that is being executed during the same time period.

If subroutine ISRI is expanded to include a status test plus logic to compute the timer constant that will compensate for timing slews, the new expanded version of ISRI might easily take 200 J.ls to execute. Under these circumstances the microprocessor system would spend a significant amount of its time merely moving data between memory and an 1/0 port.

In all but the simplest 1/0 transfer applications, therefore, DMA becomes the preferable way of moving data between memory and external devices.

8.4.2 Programming DMA

The actual programming steps required in order to initiate a DMA operation are simple, as follows:

LI ADLO LOAD BUFFER STARTING OUT BUFA ADDRESS INTO ADDRESS

1/0 PORTS

LI ADHI

OUT BUFB

LI CTLO LOAD LOW ORDER BYTE OF BYTE COUNT

OUT BUFC

LI CTRL LOAD HIGH ORDER 4 BITS OF BYTE COUNT

OUT BUFD PLUS CONTROL BITS Symbols must be equated as follows:

1) The 1/0 port addresses, BUFA, BUFB, BUFC and BUFD

liD PORT BUFD 7 6 5 4 3 2

o

are given in Table 2-2 for the four 3854 DMA devices that may be present in an F8 microprocessor system.

Whether a DMA device uses the first, second, third or fourth set of addresses is a function of device hard-ware configuration and of no concern to the program-mer, so long as the correct port addresses are used.

2) ADLO and ADHI represent the low order and high order bytes of the beginning address of the memory buffer into which data will be written, or from which data will be read.

3) Data buffers may be up to 4,096 bytes long. CTLO represents the low order eight bits of the buffer length, as illustrated in Figure 8-4. CTRL provides the controls which select DMA options and also the high order-four bits of the buffer length, as illustrated in Figure 8-4.

The following instructions will initiate 256 bytes of data being written into a memory buffer, where the data rate is con-trolled by the external device. The memory buffer starting address is H'A280'. The first DMA channel is used.

U H'8D' OUTPUT LOW ORDER BYTE OF ADDRESS

OUT H'FO'

LI H'A2' OUTPUT HIGH ORDER BYTE OF ADDRESS

OUT H'Fl'

LI H'OO' OUTPUT LOW ORDER BYTE OF COUNT

OUT H'F2'

LI H'Cl' OUTPUT HIGH ORDER 4 DIGITS OF COUNT (1) OUT H'F3' AND CONTROL DIGIT (C).

liD PORT BUFC

7 6 5 4 3 2 o ^{Bit No.}

I I I I I I I I I

1 - Data transfer continues until bit 7 is reset to O.

o -

- Data is transferred from an external device to main memory_

o - Halt DMA operation 1 - Start DMA operation

Fig. 8-4. How BUFC and BUFD are used to Control DMA Operations

8-10

8.4.3 Catching DMA on the Fly

There are many applications in which data will be transferred via DMA at unpredictable rates. For example, in communi-cations applicommuni-cations, data may come over a telephone line at a fixed baud rate, but the length of messages and the period when no data is being transferred may be completely random.

Under such circumstances it is very useful if a program can start and stop DMA operations or interrogate the buffer counter to find out how much data has been transferred via DMA since the last interrogation. The following program sequence catches DMA on the fly, in a way that would be well suited to random data transfer rates in communications applications:

*SUBROUTINE TO INITIALIZE DMA WITH H'FF' IN THE BYTE

*COUNTER. THE DATA BUFFER STARTS AT H'2000' DMA LI H'OO' OUTPUT BUFFER STARTING

ADDRESS

S2

OUT H'FO' L!

OUT LI OUT LI OUT POP

H'20' H'F1' H'FF' H'F2' H'CO' H'F3'

OUTPUT BYTE COUNTER

*MAIN PROGRAM TO HANDLE COMMUNICATIONS DATA

*TRANSFERRED VIA DMA

M1 M2 M3

PI

, _LI;:)

...

OUT IN COM

DMA

o

H'F3' H'F2'

M4 LR O,A

INITIALIZE DMA

STOP DMA DATA TRANSFER LOAD BYTE COUNT INTO SCRATCHPAD BYTE 0 (instructions to process data follow here)

8-11

Instruction steps to initiate DMA are pClckaged as a subrou-tine labeled DMA. The buffer length output is H'FF'. As this buffer length is counted down, the number of bytes trans-ferred via DMA can, at any time, be determined by reading the contents of 1/0 port F2 into the accumulator and com~

plementing. The control digit C starts data flow via DMA from the external device (assumed to be a communications interface) to the memory buffer, beginning at H'2000'.

The main program starts by initializing DMA via a call to subroutine DMA. At some later point in the program, in-structions M1 and M2 are executed in order to load the code digit 0 into 1/0 port F3 and thus stop DMA transfers. Instruc-tions M3 through M4 determine the number of bytes that have been transferred via DMA, since DMA was initiated, and loads this byte count into scratch pad register O. Instruc-tions will now follow to move the number of bytes received to some other memory location where the data can be pro-cessed. Subroutine DMA will then be recalled to re-initialize DMA data transfers. After data has been processed execution will branch back to instruction M 1 and so the program will continue processing whatever data has been transferred in each time interval.