ASD - DECIMAL ADD, SCRATCHPAD TO ACCUMULATOR

The ASD instruction is similar to the AMD instruction, except that instead of adding the contents of the memory byte ad-dressed by the DCO registers, the content of the scratchpad byte addressed by operand (Sreg) is added to the accumulator.

FORMAT:

DECIMAL ADD:

AI H'66' ALWAYS PRECEDES ASD FOR ADDITION

[LABEL] ASD Sreg Sreg is defined in Table 6-2.

DECIMAL SUBTRACT:

[LABEL]

COM ASD AI ASD

Sreg H'66' ONE

STATUS CONDITIONS:

ALWAYS PRECEDES ASD FOR SUBTRACTION

SCRATCHPAD BYTE ONE CONTAINS H'01'

The status bits have the same significance as they do for the AMD instruction.

EXAMPLES:

DECIMAL ADD:

Assume the accumulator contains H'42', the ISAR contains 0'S4', and scratchpad register 0'S4' contains H'83'.

After the instruction sequence:

AI H'66' ASD D

is executed, the accumulator will contain H'2S'. ISAR will contain 0'S3'.

There is a carry, so CARRY

=

1.

Other status indicators are modified, but their condition is not significant.

[LABEL] OP t,DEST

OP is one of the mnemonics BF or BT.

is a condition specification, as given in Table 6-S for BT, or in Table 6-4 for BF.

DEST is as described above.

Relative branching is performed within a range of 127 ad-dress locations forward and 128 adad-dress locations behind the address of the branch instruction's second byte.

All branch instructions are similar in operation, the only dif-ference is the conditions under which a branch occurs. The instruction BC - BRANCH ON CARRY will be used as an example of how the branch instructions are executed.

When a BC instruction is executed a branch occurs to the instruction whose label is specified in

Be

instruction operand, but only if the Carry bit is set at the time the BC instruction is executed.

First, consider a BRANCH FORWARD as indicated in the following instruction sequence:

Memory Address H'4ADE' H'4ADF' H'4AEO' H'4AE1'

1

H'4B5F'

J

Object Source

Code Program

H'88' ... _ - - - A M

H'82'iIIIC BC LOOP

H'7F'

-r:~

•

.---~

--L

Displacement = H'7F'

H'1F' LOOP INC

Fig. 6-1. Generation of a Displacement Object Program Byte in

6.7

BRANCH INSTRUCTIONS Response to a Forward Branch The Branch instruction is used to modify a program's

instruc-tion execuinstruc-tion sequence by altering the contents of the pro-gram counters, PCO. In a conditional branch instruction, alteration occurs when specified branch test conditions are met. In an unconditional branch instruction, a branch occurs simply as the result of the execution of the instruction.

All branch instructions are two-byte instructions. The first byte is the object code of the instruction mnemonic. The sec-ond byte is a displacement which is added to the program counter if a branch occurs.

Conditional branch mnemonics: BC, BF, BM, BNC, BNO, BNZ, BP, BR7, BT, BZ

Unconditional branch mnemonics: BR FORMATS:

[LABEL] OP DEST

OP is one of the mnemonics BC, BM, BNC, BNO, BNZ, BP, BR7 or BZ.

DEST is an expression which evaluates to the memory ad-dress to which a branch may occur. Frequently DEST labels the instruction to which a branch may occur.

6-5

Figure 6-1 illustrates source and consequent object program.

Assume the Carry bit is set as a result of the AM instruction execution and the contents of the program counters, PCO, are equal to H'4AEO', subsequent to the BC instruction operand fetch. A branch to H'4BSF' is indicated by the BC instruction as follows:

The displacement vector between H'4BSF' and H'4AEO' must be added to the program counters. This vector (+D'127') will have been calculated by the assembler and stored in the second byte of the BC instructions object code.

When a single byte displacement vector is added to the con-tents of the program counters, the most significant bit of the single byte displacement vector is propagated through the high order eight bits of the addition as follows:

Bit No:

H'4AEO' H'7F' H'4BSF'

1S 14 13 12 11 10

9

8 7 6 S 432 1 0

o

1 0 0 1 0 1 0 1 1 1 0 0 0 0 0

o

⁰ 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1

Next, consider a BRANCH BACKWARD as indicated in the following instn..:ction sequence:

Memory Fig. 6-2. Generation of a Displacement Object Program Byte in

Response to a Backward Branch

Assume the carry bit is set and the program counters con-tain H'B692', subsequent to the BC instruction operand fetch.

A branch to H'B612' is indicated by the BC instruction as follows:

The displacement vector between the address of the second byte of the BC instruction and the address of the instruction labeled LOOP is added to the PCO registers. The displace-ment vector will have been calculated by the assembler and stored in the second byte of the BC instruction object program.

In the case of a BRANCH BACKWARD, the negative displace-ment will be a two's compledisplace-ment number. Since the high order (sign) bit of the displacement is 1, it will be propagated through the high order eight bits of the addition as follows:

OPERAND STATUS FLAGS TESTED t OVF ZERO CARRY SIGN

Table 6-4. Branch Conditions for SF Instruction

6-6

I

I

Table 6-3 lists the branch instruction mnemonics and the con-ditions under which a branch will occur. Table 6-3. Branch Conditions

DEFINITION COMMENTS

Branch if negative and no overflow

Branch if no overflow and no carry Branch if no overflow,

no carry & negative Branch if no overflow

and not zero

Same as t=9 Branch if no overflow,

no carry & not zero

Same as t=B

7.1.4, 7.2.2, 7.3.4

7.1.1,7.1.2,8.2.7,

17.2.1, 7.2.2, 7.3.41

OPERAND STATUS FLAGS TESTED

t ZERO CARRY SIGN

0 0 0

1 0 0

2 0 1

3 0 1

4 1 0

5 1 0

6 1 1

7 1 1

Table 6-5. Branch Conditions for BT Instruction

6.7.1 BF - Branch on False

The BF - BRANCH ON FALSE instruction will branch if the status bits selected by t in Table 6-4 are all reset. Selected bits are identified in Table 6-4 by 1 under "Status Flags Tested"; selected status bits must all be zero. Unselected status bits are ignored.

6.7.2 BT - Bianch on Tfue

The BT - BRANCH ON TRUE instructions will branch if any test conditions defined by t in Table 6-5 are met.

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