Data transfers to the SCSI bus are done through 80186 DMA transfers and a DMA state machine. The 80186 DMA transfers are not synchronized. This means that the DMA cycle (read the source, write the destination) will occur at full processor speed regardless of the validity of the data on the bus. The purpose of the state machine is to insert wait states in the read cycle of the DMA cycle until the SCSI bus REQ(H) line is asserted, indicating that the target is ready to send or receive another byte. Figure 9-5 shows a SCSI data transfer.
Mass Storage Controller Board-8560/8561/8562 Service MSC Hardware
TO
I
T1I
T2I
T3I
TOI
T1I
T2I
T380186 Slate
I
S1I
S2I
S3I
S4I
S1I
S2I
S3I
S4I
S1I
S2I
S3I
SWI
SWI
SWI
S4I
S1I
S2I
S3I
S4I
S1I
S2I
S3I
S4I
ClK
INPUTS :
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REQ I I I ~
S6W~hY~----~~---~----~~~----~~~~--~~~r---~
SCSIDMAWR _+-1 _ _ _ _ _ --+ _ _ _ ..J
1 ,
80186RD _~~I
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OUTPUTS
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ACK_~ _ _ _ _ _ ~ _ _ _ _ _ ~_~
BE--~---~----~
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SCSIWAIT
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DISK WRITE DISK READ
READ MEM READ SCSI
WRITE SCSI WRITE MEM
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READ MEM WRITE SCSI
READ SCSI WRITE MEM
4759-26
Fig. 9-5. SCSI data transfer.
Inputs. The state machine timing diagram is shown in Figure 9-4. The input S6 comes directly from the 80186. This input is valid in CPU states S2, S3, SW and S4 of a CPU read or write cycle and indicates that a DMA cycle is in process when asserted.
The REQ(H) input is a logical OR of three Signals: the SCSI bus REQ(H), a firmware programmable request used to re-set the state machine after a transfer takes place, and a timeout signal. The REQ(H) input is synchronized to the state machine clock.
Outputs. The outputs of the state machine are BE(L), ACK(H) and SCSIWAIT(L).
The ACK(H) signal is asserted in the read cycle of the DMA transfer and dropped one state after the REQ(H) input has been deasserted.
The BE(L) signal enables the transceiver register outputs in the 2908s onto the SCSI bus. BE(L) will be active during both SCSI reads and writes. Therefore, before a SCSI read takes place, the firmware must write OOH to the SCSI data lines.
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MSC Hardware
Hardware Registers
~ ~
The following paragraphs describe the various MSC Board hardware registers. have the following definitions:
DO output of the SCSI arbitration state machine. When set, the MSC Board has won mastership of the SCSI bus.
This bit provides readback of the flexible interface signal, DKCHG(H). When set, it indicates that the door of the flexible drive has been opened, resulting in a possible change of disks.
This bit is the diagnostics signal DIAGS(H). Its pur-pose is described in the discussion on diagnostics.
This bit is the diagnostics signal QBUSEN. Its pur-pose is described in the discussion on diagnostics.
This bit, when cleared, resets both the SCSI arbitra-tion state machine and the SCSI DMA state machine.
This bit sets or resets the SCSI bus SEL(H) line.
Unused.
When set, this bit tells the SCSI arbitration state machine to arbitrate for the SCSI bus.
Qbus Status Register. The Qbus Status Register can be accessed through address 4180H. It is composed of flip-flops U1080, U1040 and U4110B for writing and U1090 for read back. It is 8 bits wide. Although it is called the Qbus status Register, some bits are not concerned with the Qbus.
Its bits have the following definition:
DO
D1
9-10
This bit, when set, indicates that the Device Register has been written. DO can be set or cleared by writing to the register.
This bit, when set, indicates that the Qbus timed out during a Qbus DMA transfer. D1 can be set or cleared by writing the register.
D2
Mass Storage Controller Board-8560/8561/8562 Service
This bit, when set, configures the Flexible Disk Con-troller Chip to read and write single-density disks.
When cleared, the Flexible Disk Controller Chip as-sumes a double-density disk is in the drive.
This bit is read only. When set, D3 indicates that an interrupt to the Qbus is pending.
This bit is read only. When set, D4 indicates that a parity error occurred when reading or writing LSI-11 memory.
This bit is read only. When D5 is set, a double-sided disk is in the flexible disk drive unit. When cleared, a single-sided disk is in the drive.
This bit can be read or written. When set, D6 selects flexible disk drive number 1.
This bit provides read back for the INTRQ output of the WD2797.
Diagnostics Register. The Diagnostics Register is used by the diagnostics firmware to test the Qbus in~erface .. A full description of how to use the register for diagnostic pur-poses is given in the section on board test hardware.
The Diagnostics Register can be accessed through address 4300H. It is composed of U3160 for writing and U2160 for readback. Its bits have the following definitions:
DO the Qbus DMA state machine.
When written, this bit is the diagnostics signal
Mass Storage Controller Board-8560/8561/8562 Service
D6 When written, this bit is the diagnostics signal, IAKI.
When read, D6 specifies the SCSI ID for the MSC Board. This bit can be configured to be a logic low or high through a jumper. D6 is interpreted as follows:
D7
This section describes interactions between the MSC hard-ware, the MSC operating firmhard-ware, and the TNIX Operating System.
Simplified Disk Access Operation
When you enter a command from the terminal requiring the TNIX operating system to access a file (either to read or to write), a sequence of steps occurs. During that sequence, TNIX generates a command buffer in the 8560 memory and stores the starting address of that buffer in a hardware reg-ister on the MSC . TNIX then informs the MSC that it can access the command buffer and execute the command it contains. Here is a simplified description of this sequence:
NOTE
Except where noted, this description is valid for both read and write operations. Only the direction of trans-fer diftrans-fers.
1. TNIX searches the disk directories during a read opera-tion until it finds the specified file and identifies its
3. TNIX stores the command buffer address in the Device Register located on the MSC Board. (This register is described earlier in this section.)
Firmware/Hardware Interactions
4. The 80186 on the MSC Board performs a DMA opera-tion and reads the buffer contents. (Since the Device Register is not on the 80186 bus, the 80186 cannot access this register directly).
5. The MSC firmware stores the command buffer instruc-tions in the command queue for the accessed disk drive and informs TNIX that the instructions have been received.
6. The command queue may already contain other previ-ously entered commands. To minimize seek time, the MSC firmware changes the order in which commands are executed. (Seek time is the time needed by the disk drive to move the heads over the specified disk block.) When the command is executed, the MSC firmware calcu-lates the physical disk address of the requested block (file).
The MSC then moves the disk heads over the specified interrupt to the LSI-11 informing TNIX that the block of data is now stored at the appropriate place.
Hardware Devices
The following text describes hardware devices accessed by the MSC operating firmware. The four hardware devices are: the Xebec S1410 Disk Controller, the Device Register, the WD2797 Flexible Disk Controller Device, and the Seven-Segment Display device. A short description of each hardware device follows.
The Xebec 51410 Disk Controller
The Xebec S1410 Disk Controller Board interfaces the MSC Board to the hard disk drive unit. The 80186 sends com-mands to the Xebec Disk Controller and receives data and status information. Section 10 of this manual provides a more detailed description of the Xebec S1410 Disk Control-ler Board.
Device Register
The Device Register is the hardware communications link between the 8560's LSI-11 and the MSC's 80186 proces-sor. The Device Register is located on the MSC Board.