6000 363848433lDATTAB: DFB "68HCll/PSD311 UP" ,OOH i
6011 54494D4F54CREDITS: DFB 6023 4l4E544543 DFB 6037 524F434B20 DFB
"TIMOTHY E. DUNAVIN"
"ANTEC - ANIXTER MFG."
___________________________________
f==:F~__________________________________ _
--==
~mPSD3XX - Application Note 019'
;PARALLEL I/O CONTROL REGISTER
;PORT C DATA REGISTER (ADO - AD7)
;TIMER COMPARE FORCE REGISTER
;OUTPUT COMPARE 1 MASK REGISTER
;PULSE ACCUMULATOR CONTROL REG
;PULSE ACCUMULATOR COUNT REG
;SPI CONTROL REGISTER
;SPI STATUS REGISTER
;A/D CONTROL/STATUS REGISTER
;A/D RESULT REGISTER 1
AppendixB.
PS03XX - Application Note 019
OPTION: EQU
SYSTEM CONFIGURATION OPTIONS ARM/RESET COP TIMER CIRCUITRY EEPROM PROGRAMMING REGISTER HIGHEST PRIORITY INTERRUPT
RAM AND I/O MAPPING REGISTER (NEW ADD.) FACTORY TEST REGISTER
CONFIGURATION CONTROL REGISTER
;
PSD3XX - Application Note 019 C079 l8CE6000 C07D BDCOCC
;SEND INSTRUCTION
;5mS DELAY
;TlME DELAY
;ENTRY MODE SET
;SEND INSTRUCTION
;5mS DELAY
;TlME DELAY
;DISPLAY CURSOR HOMEI
;4.0mS DELAY
;RESET WATCHDOG TIMER
;RETURN FROM SUB.
_________________________________________ r3f=aF~ ______________________________________ ___
=-~~B
1-138
AppendixB.
PSD3XX - Application Note 019
i*******
PS03XX - ApplicatiDn NDte 019
C14F 133080FC CONV1: ADCTL,80H,CONV1 ;WAIT HERE TILL CONVERSION COMPLETE
;RETURN FROM SUB.
AppendixB.
PS03XX - Application Note 019
i***************************
PSD3XX - Application Note 019
AppendixB.
Core System Software for Cable Tester Design (Cont.)
;
C170 8102 DOIT20: CMPA #KEY3 3 KEY?
Cl72 2601 BNE DOIT30 IF NOT, GOTO DOIT30
C174 3B RTI RETURN FROM INT.
;
C175 8103 DOIT30: CMPA #KEYA ;A KEY?
Cl77 2601 BNE DOIT40 ;IF NOT GOTO DOIT40
C179 3B RTI ; RETURN FROM INT.
;
c17A 8104 DOIT40: CMPA #KEY4 ;4 KEY?
C17C 2601 BNE DOIT50 ;IF NOT GOTO DOIT50
C17E 3B RTI ; RETURN FROM INT.
;
C17F 8105 DOIT50: CMPA #KEY5 ;5 KEY?
C18l 2601 BNE DOIT60 ;IF NOT GOTO DOIT60
C183 3B RTI ; RETURN FROM INT.
;
C184 8106 DOIT60: CMPA #KEY6 ;6 KEY?
C186 2601 BNE DOIT70 ;IF NOT GOTO DOIT70
C188 3B RTI ; RETURN FROM INT.
;
C189 8107 DOIT70: CMPA #KEYB ;B KEY?
C18B 2601 BNE DOIT80 ;IF NOT GOTO DOIT80
C18D 3B RTI ; RETURN FROM INT.
;
C18E 8108 DOIT80: CMPA #KEY7 ;7 KEY?
C190 2601 BNE DOIT90 ;IF NOT GOTO DOIT90
C192 3B RTI ; RETURN FROM INT.
;
C193 8109 DOIT90: CMPA #KEY8 ;8 KEY?
C195 2601 BNE DOIT100 ;IF NOT GOTO DOIT100
C197 3B RTI ; RETURN FROM INT.
;
C198 8l0A DOIT100: CMPA #KEY9 ;9 KEY?
C19A 2601 BNE DOITllO ;IF NOT GOTO DOITllO
C19C 3B RTI ; RETURN FROM INT.
;
C19D 8l0B DOITllO: CMPA #KEYC ;C KEY?
C19F 2601 BNE DOIT120 ;IF NOT GOTO DOIT120
C1Al 3B RTI ;RETURN FROM INT.
;
C1A2 8l0C DOIT120: CMPA #KEYZ 1* KEY?
C1M 2601 BNE DOIT130 ;IF NOT GOTO DOIT130
C1A6 3B RTI ;RETURN FROM INT.
;
C1A7 8l0D DOIT130: CMPA #KEYO ;0 KEY?
ClA9 2601 BNE DOIT140 ;IF NOT GOTO DOIT140
CIAB 3B RTI ;RETURN FROM INT.
C1AC 8l0E DOIT140: CMPA I #KEYY ;# KEY?
C1AE 2601 BNE DOIT150 ;IF NOT GOTO DOIT150
CIBO 3B RTI ; RETURN FROM INT.
;
C1B1 810F DOIT150: CMPA #KEYD ;D KEY?
C1B3 2600 BNE DOIT160 ;IF NOT GOTO DOIT160
C1B5 3B DOIT160: RTI ;RETURN FROM INT.
;
i*******************************
,
.* XIRQ SERVICE ROUTINE * i*******************************1-142
tal;
AppendixB.
Core System Software for Cable Tester Design (Cont.)
ClB6 3B
ClB? 3B
FFCO FFCO FFD6 Cl54 FFD8 Cl55 FFDA Cl56 FFDC Cl5?
FFDE Cl58 FFEO Cl59 FFE2 Cl5A FFE4 Cl5B FFE6 Cl5C FFE8 Cl5D FFEA Cl5E FFEC Cl5F FFEE Cl60 FFFO Cl6l FFF2 Cl62 FFF4 ClB6 FFF6 ClB?
FFF8 COOO FFFA COOO FFFC COOO FFFE COOO
0000
PS03XX - Application Note 019
NOMASK: RTI iRETURN FROM INT.
i
i*******************************
i* SWI SERVICE ROUTINE * i*******************************
INTER: RTI i RETURN FROM INT.
i
i***********************************
i* RESET AND INTERRUPT VECTORS * i***********************************
ORG OFFCOH i
RES: DFS 11*2 iNOT USED
SERCOM: DWM SCOM i SERIAL COMM. INT.
SPISTC: DWM TRANC iSERIAL TRANSFER COMPLETE PAlE: DWM PULSEE iPULSE ACCUMLATOR INPUT EDGE PAOV: DWM PULSEO iPULSE ACCUMULATOR OVERFLOW TOV: DWM TIMEO i TIMER OVERFLOW
TOCP5: DWM COMP5 iTlMER OUTPUT COMPARE 5 TOCP4: DWM COMP4 iTlMER OUTPUT COMPARE 4 TOCP3: DWM COMP3 iTIMER OUTPUT COMPARE 3 TOCP2: DWM COMP2 iTlMER OUTPUT COMPARE 2 TOCPl: DWM COMPl iTlMER OUTPUT COMPARE 1 TICP3: DWM ICOMP3 iTlMER INPUT COMPARE 3 TICP2: DWM ICOMP2 iTlMER INPUT COMPARE 2 TICPl: DWM ICOMPl iTlMER INPUT COMPARE 1 RTlME: DWM REALT i REAL-TIME INT.
IRQ: DWM DOlT iTlMER/VIA INT.
XIRQ: DWM NOMASK iNON-MASKABLE INT.
SWI: DWM INTER iSOFTWARE INT.
lOT: DWM START iILLEGAL OPCODE TRAP (START OVER) COPS: DWM START i COP FAILURE (RESET)
COPSl: DWM START iCOP CLOCK MONITOR FAIL (RESET) RESET: DWM START iRESET
i
i************************************************
END iTHE END!!!!!
---~~~jf---1·143PS03XX - Application Note 019
-1--1-#---~Jr~~---iFliIliI4E6J
Application Note 020
Benefits of 16-Bit Design with PSD3XX
By Ching Lee
Embedded controller architecture has been evolving from 4-bit, 8-bit to 16-bit through the years. The increase in the data bus bandwidth is a natural progression for microcontrollers to achieve higher performance. Today, 16-bit embedded controllers such as the 80C196 and 683XX families provide excellent performance at reasonable cost. Yet many designers are weary of the cost of higher chip count, more board space and power consumption in 16-bit applications and prefer to stay with 8-bit designs. Some microcontroller manufacturers tackle this problem by introducing processors with 16-bit internal architectures but have 8-bit external data busses. Later additional enhancements such as dynamic bus sizing provide the choice of selecting either an 8 or 16-bit bus for further cost reduction. This compromise There is no one standard 16-bit
architecture, especially in the field of embedded controller applications. For a typical 80C196 design, the basic building block consists of two address latches (74AC373), address decoding logic (with PAL or discrete logic), program memory (EPROMs), data memory (one or more SRAM), and I/O devices.
Figure 1 is the schematic of such a system.
In this design, 64K bytes of program memory/EPROM, and a 2K byte SRAM for scratch pad are required. Since the 80C196 has only 64K byte memory space, the INST signal provides the paging capability, with program memory residing in the first 64K page while SRAM and I/O devices occupy the second page. The I/O section consists of one output port (74AC374) and other peripheral devices.
The chip select signals for the I/O devices and memory are connected directly from the decoding PAL outputs. The processor's data bus width is determined by the type of
certainly increases the performance; it is still not as good as a true 16-bit implemen-tation.
With the introduction of the PSD3XX family of field programmable microcontroller peripherals from WSI, there is no reason not to use 16-bit microcontrollers. The PSD3XX provides an integrated solution in a single chip, which includes user configurable I/O ports, Chip Select outputs, logic replacement, Page Register, Programmable Address Decoder (PAD), EPROM and SRAM. The PSD3XX is a perfect match for 16-bit microcontroller applications. In this application note, we will look at some of the advantages of 16-bit designs, and how PSD3XX interfaces to microcontrollers such as the 80C196 and 68302.
bus cycle. EPROM accesses are 16-bits wide, SRAM is 8-bits while I/O bus cycles can be 8 or 16-bits, depending on the device being accessed. The BWIDTH output from the PAL informs the processor what type of bus width is to be expected for that particular cycle.
An I/O device usually takes longer time to complete the bus cycle. Let us assume, in this case, I/O devices require 3 wait states with the exception of the I/O latch. The configuration register of the 80C196 is then programmed to insert 3 wait states.
Whenever there is an I/O bus cycle, the READY output signal from the PAL goes low to activate the processor's wait state control to insert the programmed amount of wait state. For memory bus cycles, no wait state is inserted.
1-145