836 837 838 , 0268 , 026A , 026D
839 840 841 , 0270 , 0272 , 0275
842 843 844 845
Notes: 1.
2.
7400 900000 120000
7400 900000 120000
}
/* Init DCC & SCR registers */
init_dsl_hdsl_dcc_scr();
MOV A,#$BYTE3 init dsl hdsl dcc scr MOV DPTR,#REFFN inIt dsl hdsl dec scr
LCALL ?X_CALL_LI8 - - -
-/* Init Master/Slave Polynomial */
init_msJloly();
MOV A,#$BYTE3 init_msJloly MOV DPTR,#$REFFN init_msJloly LCALL ?X_CALL_LI8
$Byte 3 is a directive that addresses the "page" of the specified function.
$REFFN Addresses the 16-bit offset of the function.
MODULE TITL RSEG
?BANK SWITCHER L18
'8051-- C - BANK-SWITCHER' RCODE
j---j
L18.S03
-Function (s) : Banked switched CALL and RET
Must be tailored for actual bank-switching hardware.
In the sample system the PI port was used.
version: 4.00 [IANR]
j---j
j---i
Call a non-local function
j---;
Inputs:
Stack: 16-bit return address DPTR: 16-bit function-address A: 8-bit page address
j---;
The above Archimedes code is courtesy of Jeff Fayne, Tellabs, Inc.
-1--9-~---~~~~---Archimedes Code (Cont.)
PSD3XX - Application Note 015
PUBLIC
?X CALL LlB
Save old bank
PUSH Pl
Bank-switch
MOV PI,A
Go to function
CLR A JMP @A+DPTR
;---;
Leave current function
i---;
Input:
stack: 24-bit return address
i---;
PUBLIC ?X RET LlB
?X RET LIB:
Bank-switch
POP Pl
Return
RET END
---fjfjf~~---'f!ffJ!R5.,iE 1·93
PS03XX - Application Note 015
Conclusion
The PSD3XX page register system can greatly assist designers of systems requiring large memory spaces with 16-bit address buses. The PSD3XX offers capability not found in most discrete page register implementations. The capability to define global resources as well as page-specific resources enables the designer to implement the paging technique most suitable for the application.The page register is included in the PSD302, PSD312, PSD303 and PSD313 devices, all of which are pin compatible
with one another. This provides the capability of expanding the memory size as required even after a system has been designed. The designer can simply drop the new, and larger, PSD3XX into the same footprint as the old, and update the software to add more memory pages. This capability can be important for product feature additions after a design is complete. Since the system is fully programmable, it may be updated and changed anytime.
---wrJr~~---
1-94!FEE
.=~Application Note 016
Power Considerations In The PS03XX/3XXL
By Jeff Miller
The PSD3XX is a configurable microcon-troller peripheral integrating programmable logic, EPROM and SRAM technologies into a single piece of silicon. It has been used extensively in microcontroller applications around the world by virtue of its high level of integration, configurability and ease of use. This integration makes possible the design of very compact microcontroller systems, enabling the user to squeeze a great deal of functionality into a very small space. Thus, the PSD3XX has found its way into many small hand-held and/or battery operated applications such as cellular phones, medical instrumentation and laptop or notebook computers which usually require, in addition to small space, a very low power consumption.
The PSD3XX family is based on a patented high-performance CMOS technology and, The PSD3XX contains several modules internally, each of which can be considered a power consumer when in operation.
These modules include the PAD,
(Programmable Address Decoder)EPROM and SRAM blocks. The key to reducing the power used by the PSD3XX is to reduce the power used by each of these modules individually.
Under normal operation, several of the functional modules may be operating, while others may be standing by. A module in stand by uses much less power than one that is active. For example, whenever the SRAM is not being actively used, it is disabled and therefore consumes less power. This is also true of the PAD. A PAD term which is active expends more power than one which is inactive. This would also be true of the EPROM. However, in some PSD3XX models, the EPROM is always active, in which case it will always draw power. This is done in order to provide the best access time possible for the EPROM.
The Low Power family of PSD3XXs does not keep the EPROM enabled at all times,
like other CMOS devices, requires very low power consumption even when no particular effort is made to minimize the PSD3XX power. But, when some special care is taken during the programming and configuration of the device, power can be reduced even further, making the PSD3XX even more valuable in these power-sensitive applications. This application note will describe the methods which can be used to reduce the PSD3XX power consumption in both active and stand-by modes. It makes sense to use some of these techniques even when low power is not a primary design requirement since they are easy to implement and require no additional expense. We believe that proper implementation of the material in this note will make the PSD3XX an invaluable member of any low-power microcontroller system.
and thus the designer can save power by minimizing the time during which the EPROM is accessed. Use of this feature does impact the speed of the PSD3XX EPROM, which results in the loss of the 120 ns speed grade. There are other methods of reducing EPROM power even when the EPROM is enabled. These will be discussed in detail later in this note.
When the time that each PSD3XX function is kept in standby mode is maximized, the power expense is minimized.
There is a way to place the entire PSD3XX into the standby mode at once, thereby reducing power usage to the bare minimum. This can be done through the use of the CSI (Chip Select Input) pin.
When the PSD3XX is deselected by the CSI pin, the entire part enters the standby mode using only about 50 ~A of current.
While in this mode, the PSD3XX is incapable of performing any functions, including PAD logic equations, but this is an excellent method of reducing system power in designs which have low active duty cycles.
1-95