This section gives the format of the program accessible registers of the Series 60 Level 66 Controller (SCU), the Level 68 System Controller (SC), and their associated memory.
SYSTEM CONTROLLER ILLEGAL ACTION CODES
The following are illegal action codes for the SC.
ILLEGAL ACTION CODES
CPU fIt
nonexistent address.
stop on condition. (Level 68 only)
illegal command.
store not ready.
nonexistent address.
not used.
illegal command.
store not ready.
SYSTEM CONTROLLER REGISTERS FORMAT
The read system controller register instructions and set system controller register (rscr and sscr) provide the ability to read several registers in SCs and SCUs. The effective absolute address of the instruction selects the SC (or SCU) to be referenced by referring to the port address assignment switches.
Bits 3-14 of the instruction address are sent to the SC (or SCU) to specify the register to be referenced. Bits 15-17 are not interpreted since they are used in port selection for normal data and instruction fetches when port interlace is being used. The rscr instruction reads data into the combined A and Q registers of the processor. The sscr instruction sets data from the A and Q registers.
System Controller Mode Register (rscr/sscr PL/I declaration (scr.incl.pI1)
dcl 1 scr_mr aligned,
(2 pad1 bit(50) ,
2 identification bit(4), 2 TS_strobe_margin bit(2), 2 GO_strobe_margin bit(2), 2 ANSWER_strobe_margin bit(2), 2 DA_Strobe_margin bit(2), 2 EOC_strobe_margin bit(2), 2 PLUS_5_VOLT_margin bit (2) , 2 parity_override bit(1), 2 parity_disable bit(1), 2 store_lA_disable bit(1), 2 ZAC_parity_error bit(1), 2 SGR_accepted bit(1),
2 pad2 bite 1) unal;
Upper Half (A register):
a
0
ALL ZEROS
Lower Half (Q register):
3 4 5 5 5
6 9
a
3 4ZEROS ID
OOOOOX)
MODE REG
3 5
7 1
Figure 2-1. Controller Mode Register (rscr/sscr OOOOOX) Data Format
Legend:
ID (scr.mr.identification) controller ID code.
0000
=
8034, 8035 0001=
Level 68 SC 0010=
Level 66 SCUMODE REG these fields are used only by T&D.
REGISTERS FORMAT 2-2 AN87
System Controller Configuration Switches (rscrlsscr 00001X) Note that the configuration switches of an SC cannot be set.
PL/I Declaration (scr.incl.pI1) dcl 1 scr_cfg1
2 addr_offset 2 port_no 2 port_enable 2 pima
BlalblADRl PORT
I I I I
REGISTERS FORMAT
Meaning
(scr_cfg1.mode_a/b) state of store AlB.
000
=
online.(scr_cfg1.int) interlace flag.
o =
stores are not interlaced.1
=
stores are interlaced.(scr_cfg1.lwr) low-order store flag.
o =
store A is low order.Meaning
ADR (scr_cfg1.addr_offset) setting of ADDRESS CONTROL OFFSET switch.
00
=
no offset.01
=
16K offset.10
=
32K offset.11
=
64K offset.PORT (scr_cfgl.port_no) 4-bit port number of the SC port through which the rscr instruction was received. Port 8 (1000) is the maintenance panel.
A, B ••• H (scr_cfg1.port_enable) port state for each of the eight SC ports.
00
=
port disabled.01
=
port in program control.11
=
port enabled.MASK A, ..• ,MASK D
(scr_cfg1.pima) EXECUTE INTERRUPT MASK ASSIGNMENT (EIMA) switch settings, i.e., port assignment for each of the four execute interrupt masks. The assigned port corresponds to the bit position within the field. Absence of a bit indicates that the mask is not assigned. Port 8 is the maintenance panel.
PL/I declaration (scr.incl.p11) dcl 1 scr_cfg2
(2 mask_a_assign 2 a_online 2 a1_online 2 b_online 2 bl_online 2 port_no 2 pad1 2 mode
2 nea_enabled 2 nea
2 int 2 lwr
2 port_mask_0_3 2 mask_b_assign 2 pad2
2 cyclic_prior 2 pad3
2 port_mask_4_?
REGISTERS FORMAT
aligned, bit(9), bit(1), bit(1), bi t ( 1 )
bit(1), bi t (4) ,
bit(1), bi t ( 1 ) bit(1), bite?), bit(1), bit(1), bit(4) , bit(9), bit(12), bite?), bit(4), bit(4)) unal;
2-4 AN8?
Upper Half (A register):
a a a 1 1 1 1 1 1 2 2 2 2 3 3 3 3
a 8 I 9 I 2 3 4 :2 6 9 a 1 2 9 3 1 2 2
I I I I I IMI IIILI PMR
I I I I I I I
MASK .n n ISIZE IAIAIBIBI PORT 1010 I NEA INlwl 0-3
I I i 1 i i 1 i I iD i ITIRI
! ! !
Lower Half (B register):
3 4 4 5 5 6 6 6 6 7
6 4 :2 6 1 3 4 1 8 1
CYCLIC i I not i I PMR
MASK B not used PRIOR I I used I I
4-7-I I
! !
Figure 2-1. SCU Configuration Switches (rscr/sscr 00001x Data Format)
Legend:
MASK A (scr_cfg2.mask_a_assign) EIMA switch setting for mask A. The assigned port corresponds to the bit position within the field. A bit in position 9 indicates that the mask is not assigned.
SIZE (scr.cfg2.size) size of lower store.
000
=
32K001
=
64K010
=
128K011
=
256K100
=
512K101
=
1M110 ::: 2M 11 1
=
4MA (scr_cfg2.a_online) store unit A online.
A1 (scr_cfg2.a1_online) store unit A1 online.
B (scr_cfg2.b_online) store unit B online.
B1 (scr_cfg2.B1_online) store unit B1 online.
PORT (scr_cfg.port_no) 4-bit port number of the SCU port through which the rscr instruction was received. This field cannot be set with the sscr instruction.
MOD (scr_cfg2.mode) program/manual mode. If this bit is a 1, all settable bits of the configuration register may be altered. This bit cannot be set with the sscr instruction.
NEA (scr_cfg2.nea_enabled and scr_cfg2.nea) _nonexistent address enable bit and nonexistent address. The first nonexistent address is 32,768 times the switch setting.
INT (scr_cfg2.int) interlace flag.
a =
stores are not interlaced.1
=
stores are interlaced.REGISTERS FORMAT 2-5 AN87
LWR (scr_cfg2.lwr) low-order store flag.
o =
store A is low-order.1
=
store B is low-order.PMRO-3 MASK B
(scr_cfg2.port_mask_0_3) port enable register for ports 0 through 3.
(scr_cfg2.mask_b_assign) EIMA switch setting for mask B. (See mask A above.)
CYCLIC PRIOR
(scr_cfg2.cyclic_prior) settings of the ("anti-hogging") switches.
cyclic port priority PRM 4-7 (scr_cfg2.port_mask_4_7) port enable register for ports 4 through 7.
System Controller Interrupt Mask Register (rscr/sscr OOON2X) PL/I declaration (scr.incl.p11)
dcl 1 scr msk
(2 interrupt_mask_1 2 pad1
2 port_mask_1 2 interrupt_mask_2 2 pad2
2 port_mask_2
Upper Half (A register):
o o
IERO-15
Lower Half (Q register):
6 3
IER16-31
aligned, bit(16), bit(16), bit(4), bit (16), bit(16), bit (4)) unal;
1 1
5 6 3 3 1 2 3
5
16
I I I
I I I
10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IPERO-3 I 16
I '
!
4
5 5 1 2
6 6 7 8 7
1
I I I
I I I
/0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01PER4-7 I
I I I
, I !
16 16 4
Figure 2-2. Interrupt Mask Register (rscr/sscr OOON2X) Data Format
Legend:
IERO-15 (scr_msk.interrupt_mask_1) program interrupt enable register
interrupts 00 through 15. for
PERO-3 (scr_msk.port_mask_1) port enable register for ports 0 through 3.
This field is not set by sscr instruction.
IER16-31 (scr_msk.interrupt_mask_2) program interrupt enable register for interrupts 16 through 31.
PER4-7 (scr_msk.port_mask_2) port enable register for ports 4 through 7.
This field is not set by sscr instruction.
REGISTERS FORMAT 2-6 AN87
System Controller Interrupt Cells Crscrlsscr 00003X)
(There is no include file for the declaration of this data.) Upper Half (A register):
o
o
5 6 1 1 3 5I I
I I
Interrupt Cells 0-15 \0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\
I I
! I
16 20
Lower Half (Q register):
6 3
5 5 1 2
7 1
I I
I I
Interrupt Cells 16-31 \0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\
16 20
Figure 2-3. Interrupt Cells (rscrlsscr 00003X) Data Format
A bit appearing in any position of the data indicates that the corresponding interrupt cell is set.
System Controller Crock Crscrlsscr 00004X)
(There is no include file for the declaration of this data.) Upper Half (A register):
I I
o o
\0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Lower Half (Q register):
3 6
0 1 2 9 0
I I
0\
I I
20
CLOCK BITS 16-51
CLOCK BITS 0-15
Figure 2-4~ System Clock (rscrlsscr/rccl 00004X) Data Format 3 5
16
7 1
36
NOTE: The rccl instruction may also be used to read the system clock. The clock in an SC cannot be set with the sscr instruction. It must be set manually. The clock in an SCU cannot be set manually. It must be set using the sscr instruction.
REGISTERS FORMAT 2-7 AN87
Store Unit Mode Register (rscr/sscr 00006X) PL/I declaration (scr.incl.p11)
dcl 1 scr _su (2 pad 1
2 ZAC_line 2 syndrome
2 identification 2 EDAC disabled 2
pad2-2 MINUS_5_VOLT_margin 2 PLUS_5_VOLT_margin 2 spare_margin
2 PLUS_19_VOLT_margin 2 pad3
2 SENSE_strobe_margin 2 pad4
2 maint_functions_enabled Upper Half (A register):
o
o
ALL ZEROS
Lqwer Half (Q Register):
6 3 ZAC
4 4 . 4 5 1 2 9 0
SYN ID
555 3 4 5
I I
I I
I al
I I
I I
aligned, bit(36), bit(6) , bit(8), bi t (4) , bit(1), bit(4), bit(2) , bit(2) , bit(2), bi t (2) ,
bit(1), bit(2) , bit(1), bit(1» unal;
MAINT
5 3
7 1
Figure 2-5. Store Mode Register (rscr/sscr 00006X) Data Format
Legend:
Meaning
ZAC (scr_su.ZAC_line) address lines.
SYN (scr_su.syndrome) failure syndrome.
ID (scr_su.identification) store unit type identification.
0000
=
high-speed core model AA1.0001
=
high-speed core model AA3.0100
=
1K chip MOS memory with EDAC enabled.1100
=
1K chip MOS memory with EDAC disabled.1111
=
4K chip MOS memory.a (scr su.EDAC disabled) this bit is turned on when EDAC is disabled.
-MAINT these fields are used only by T&D.
REGISTERS FORMAT 2-8 AN87
SECTION III