Checkstop Sources and Enables Register—HID0

The checkstop sources and enables register (HID0), shown in Figure 2-25, is a supervisor-level register that defines enable and monitor bits for each of the checkstop sources in the 601. The SPR number for HID0 is 1008.

Table 2-21. Additional SPR Encodings

SPR Number SPR Encoding

SPR(5–9)|SPR(0–4) Register Name Access

1008 11111 10000 Checkstop sources and enables register (HID0) Supervisor

1009 11111 10001 601 debug modes register (HID1) Supervisor

1010 11111 10010 IABR (HID2) Supervisor

1013 11111 10101 DABR (HID5) Supervisor

1023 11111 11111 PIR (HID15) Supervisor

Figure 2-25. Checkstop Sources and Enables Register (HID0)

Table 2-22 defines the bits in HID0. The enable bits (bits 15–31) can be used to mask individual checkstop sources, although these are provided primarily to mask off any false reports of such conditions for debugging purposes. Bit 0 (HID0[CE]) is a master checkstop enable; if it is cleared, all checkstop conditions are disabled; if it is set, individual conditions can be enabled separately. HID0[EM] (bit 16) enables and disables machine check checkstops; clearing this bit masks machine check checkstop conditions that occur when MSR[ME] is cleared. Bits 1–11 are the checkstop source bits, and can be used to determine the specific cause of a checkstop condition.

Table 2-22. Checkstop Sources and Enables Register (HID0) Definition

Bit Name Description

0 CE Master checkstop enable. Enabled if set. If this bit is cleared and the TEA signal is asserted, a machine check exception is taken, regardless of the setting of MSR[ME].

1 S Microcode checkstop detected if set.

2 M Double machine check detected if set.

3 TD Multiple TLB hit checkstop if set.

4 CD Multiple cache hit checkstop if set.

5 SH Sequencer time out checkstop if set.

6 DT Dispatch time out checkstop if set.

7 BA Bus address parity error if set.

8 BD Bus data parity error if set.

9 CP Cache parity error if set.

10 IU Invalid microcode instruction if set.

11 PP I/O controller interface access protocol error if set.

12–14 — Reserved

15 ES Enable microcode checkstop. Enabled by hard reset. Enabled if set.

Reserved

HID0

EDT ESH ECD ETD

EBD ECP EIU EPP EBA

DRF DRL PAR

EMC EHP

CE S M TD CD SH DT BA BD CP IU PP 0 0 0 ES EM LM

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

All enable bits except 15 and 24 are disabled at start up. The operating system should enable these checkstop conditions before the power-on reset sequence is complete.

Checkstop enable bits can be set or cleared without restriction. If a checkstop source bit is set, it can be cleared; however, if the corresponding checkstop condition is still present on the next clock, the bit will be set again. A checkstop source bit can only be set when the corresponding checkstop condition occurs and the checkstop enable bit is set; it cannot be set via an mtspr instruction. That is, you cannot manually cause a checkstop.

16 EM Enable machine check checkstop. Disabled by hard reset. Enabled if set. If this bit is cleared and the TEA signal is asserted, a machine check exception is taken, regardless of the setting of MSR[ME].

17 ETD Enable TLB checkstop. Disabled by hard reset. Enabled if set.

18 ECD Enable cache checkstop. Disabled by hard reset. Enabled if set.

19 ESH Enable sequencer time out checkstop. Disabled by hard reset. Enabled if set.

20 EDT Enable dispatch time out checkstop. Disabled by hard reset. Enabled if set.

21 EBA Enable bus address parity checkstop. Disabled by hard reset. Enabled if set.

22 EBD Enable bus data parity checkstop. Disabled by hard reset. Enabled if set.

23 ECP Enable cache parity checkstop. Disabled by hard reset. Enabled if set.

24 EIU Enable for invalid ucode instruction checkstop. Enabled by hard reset. Enabled if set.

25 EPP Enable for I/O controller interface access protocol checkstop. Disabled by hard reset.

Enabled if set.

26 DRF 0 Optional reload of alternate sector on instruction fetch miss is enabled.

1 Optional reload of alternate sector on instruction fetch miss is disabled.

27 DRL 0 Optional reload of alternate sector on load/store miss is enabled.

1 Optional reload of alternate sector on load/store miss is disabled.

28 LM 0 Big-endian mode is enabled.

1 Little-endian mode is enabled.

For more information about byte ordering, see Section 2.4.3, “Byte and Bit Ordering.” Note that in the PowerPC architecture, the selection between big- and little-endian mode is controlled by two bits in the MSR.

29 PAR 0 Precharge of the ARTRY and SHD signals is enabled.

1 Precharge of the ARTRY and SHD signals is disabled.

30 EMC 0 No error detected in main cache during array initialization.

1 Error detected in main cache during array initialization.

31 EHP 0 The HP_SNP_REQ signal is disabled. Use of the WRS queue position is restricted to a snoop hit that occurs when a read is pending. That is, its address tenure is complete but the data tenure has not begun.

1 The HP_SNP_REQ signal is enabled. Use of the WRS queue position is restricted to a snoop hit on an address tenure that had HP_SNP_REQ asserted.

Table 2-22. Checkstop Sources and Enables Register (HID0) Definition (Continued)

Bit Name Description

The HID0 register is set to x'80010080' by the hard reset operation. However, the state of the EMC bit depends on the results of the power-on diagnostics for the main cache array.

This bit is set if the cache fails the built-in self test during the power-on sequence.

2.3.3.13.2 601 Debug Modes Register—HID1

The 601 debug modes register (HID1) is a supervisor-level register that defines enable bits for the various debug modes supported by the 601; see Figure 2-26. The SPR number for HID1 is 1009.

Figure 2-26. PowerPC 601 Microprocessor Debug Modes Register

Table 2-23 shows bit settings for the HID1 register. Note that if both the single instruction step option is specified for the M field (b'100') and the trap to run mode exception option is specified in the RM field (b'10'), the processor iterates in an infinite loop.

Table 2-23. HID1 Register Definition

Bit Name Description

0 — Reserved

1–3 M 601 run modes

000 Normal run mode 001 Undefined. Do not use.

010 Limited instruction address compare.

011 Undefined. Do not use.

100 Single instruction step 101 Undefined. Do not use.

110 Full instruction address compare 111 Full branch target address compare

4–7 — Reserved

8–9 RM Response to address compare or single step 00 Hard stop (Stop L1 clocks).

01 Soft stop (Wait for system activity to quiesce).

10 Trap to run mode exception (address vector x'02000'), with the base address indicated in by the setting of MSR[IP]. This mode is valid for address comparisons and may produce unpredictable results when used with HID single-instruction step mode.

11 Reserved. Do not use.

Note that when HID1[8–9] = 10, the trap address of x'2000' has a base address indicated by the setting of MSR[IP]. This mode is valid for address comparisons and may produce unpredictable results when used with HID single-step mode.

10–16 — Reserved. Do not use.

17 TL When set, this bit disables the broadcast of the tlbie instruction.

18–31 — Reserved. Do not use.

HID1

0 1 3 4 7 8 9 10 16 17 18 31

Reserved 0 M 0 0 0 0 RM 0 0 0 0 0 0 0 TL 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Note that when HID1[8–9] = 10, the trap address of x'2000' has a base address indicated by the setting of MSR[IP]. This mode is valid for address comparisons and may produce unpredictable results when used with the HID single-step mode.

The HID1 register is cleared by a hard reset.