Addressing Modes and Instruction Set Summary
3.6 Branch and Flow Control Instructions
3.6.1 Branch instruction Address Calculation
Branch instructions can alter the sequence of instruction execution. Instruction addresses are always assumed to be word aligned with the 601; the processor ignores the two low-order bits of the generated branch target address.
Table 3-24. Floating-Point Move Instructions
Name Mnemonic Operand
frD,frB The contents of register frB is placed into frD.
fmr Floating-Point Move Register
fmr. Floating-Point Move Register with CR Update. The dot suffix enables the update of the condition register.
Floating- Point Negate
fneg fneg.
frD,frB The contents of register frB with bit 0 inverted is placed into register frD.
fneg Floating-Point Negate
fneg. Floating-Point Negate with CR Update. The dot suffix enables the update of the condition register.
Floating-
frD,frB The contents of frB with bit 0 cleared to 0 is placed into frD.
fabs Floating-Point Absolute Value
fabs. Floating-Point Absolute Value with CR Update. The dot suffix enables the update of the condition register.
Floating-
frD,frB The contents of frB with bit 0 set to one is placed into frD.
fnabs Floating-Point Negative Absolute Value
fnabs. Floating-Point Negative Absolute Value with CR Update.
The dot suffix enables the update of the condition register.
Branch instructions compute the effective address (EA) of the next instruction address using the following addressing modes:
• Branch relative
• Branch conditional to relative address
• Branch to absolute address
• Branch conditional to absolute address
• Branch conditional to link register
• Branch conditional to count register
3.6.1.1 Branch Relative Address Mode
Instructions that use branch relative addressing generate the next instruction address by sign extending and appending b'00' to the immediate displacement operand LI, and adding the resultant value to the current instruction address. Branches using this address mode have the absolute addressing option (AA) disabled. If the link register update option (LK) is enabled, the effective address of the instruction following the branch instruction is placed in the link register.
Figure 3-6 shows how the branch target address is generated when using the branch relative addressing mode.
Figure 3-6. Branch Relative Addressing
3.6.1.2 Branch Conditional Relative Address Mode
If the branch conditions are met, instructions that use the branch conditional relative address mode generate the next instruction address by sign extending and appending b'00' to the immediate displacement operand (BD) and adding the resultant value to the current instruction address. Branches using this address mode have the absolute addressing option (AA) disabled. If the link register update option (LK) is enabled, the effective address of the instruction following the branch instruction is placed in the link register.
0 6 7 29 30 31
18 LI AA LK
0 31
Branch Target Address
Instruction Encoding:
+
0 31 Current Instruction Address
0 6 7 29 30 31
LI 0 0
Sign Extension
Reserved
Figure 3-7 shows how the branch target address is generated when using the branch conditional relative addressing mode.
Figure 3-7. Branch Conditional Relative Addressing
3.6.1.3 Branch to Absolute Address Mode
Instructions that use branch to absolute address mode generate the next instruction address by sign extending and appending b'00' to the LI operand. Branches using this address mode have the absolute addressing option (AA) enabled. If the link register update option (LK) is enabled, the effective address of the instruction following the branch instruction is placed in the link register.
Figure 3-8 shows how the branch target address is generated when using the branch to absolute address mode.
Figure 3-8. Branch to Absolute Addressing
0 6 7 1112 16 17 30 31
16 BO BI BD AA LK
Yes
0 31
Branch Target Address
Instruction Encoding:
No
+
0 31 Current Instruction Address
0 31 Next Sequential Instruction Address
0 16 17 29 30 31
Sign Extension BD 0 0
Condition Met?
Reserved
0 6 7 29 30 31
18 LI AA LK
0 6 7 29 30 31
0 29 30 31
Branch Target Address
Instruction Encoding:
LI 1 0
Sign Extension
0 0
3.6.1.4 Branch Conditional to Absolute Address Mode
If the branch conditions are met, instructions that use the branch conditional to absolute address mode generate the next instruction address by sign extending and appending b'00' to the BD operand. Branches using this address mode have the absolute addressing option (AA) enabled. If the link register update option (LK) is enabled, the effective address of the instruction following the branch instruction is placed in the link register.
Figure 3-9 shows how the branch target address is generated when using the branch conditional to absolute address mode.
Figure 3-9. Branch Conditional to Absolute Addressing
3.6.1.5 Branch Conditional to Link Register Address Mode
If the branch conditions are met, the branch conditional to link register instruction generates the next instruction address by fetching the contents of the link register and clearing the two low order bits to zero. If the link register update option (LK) is enabled, the effective address of the instruction following the branch instruction is placed in the link register.
Figure 3-10 shows how the branch target address is generated when using the branch conditional to link register address mode.
0 6 7 1112 16 17 29 30 31
16 BO BI BD AA LK
0 16 17 29 30 31
0 29 30 31
Branch Target Address
Instruction Encoding:
No 0 31 Next Sequential Instruction Address
Sign Extension BD 1 0
Condition Met?
Yes
0 0
Figure 3-10. Branch Conditional to Link Register Addressing
3.6.1.6 Branch Conditional to Count Register
If the branch conditions are met, the branch conditional to count register instruction generates the next instruction address by fetching the contents of the count register and clearing the two low order bits to zero. If the link register update option (LK) is enabled, the effective address of the instruction following the branch instruction is placed in the link register.
Figure 3-11 shows how the branch target address is generated when using the branch conditional to count register address mode.
0 6 7 11 12 16 17 21 22 30 31
Condition Met?
0 0 30 31 LR
0 29
0 31
Branch Target Address
Instruction Encoding:
No 0 31 Next Sequential Instruction Address
Yes
19 BO BI 0 0 0 0 0 16 LK
||
Reserved
Figure 3-11. Branch Conditional to Count Register Addressing