Bus Cycle Sequence

The order in which the DDMA executes bus cycles during a transfer operation depends primarilyon the transfer protocol used and the memory, device, and operand size combination. The following descriptions of the sequence used by each protocol assumes that only one channel is active during the operation.

5.4.1.1 SINGLE ADDRESS TRANSFERS. The sequence used for this protocol is very simple.

When a request is recognized internally, the DDMA will arbitrate for the bus if necessary and exe-cute one bus cycle in response to each request. Since the operand size must match the device port size for single address transfers and one bus cycle is run for each request, the number of normally

terminated bus cycles executed during a transfer operation will always be equal to the value pro-grammed into the MTCR (unless the transfer is terminated early by the peripheral device). The se-quencing of the address bus will follow the programming of the MAC field in the SCR. If program-med for no increment, all of the bus cycles will access the same, initial address. If programprogram-med to count up, each successive bus cycle will access the address one operand size beyond the last cycle in a linear fashion.

5.4.1.2 DUAL ADDRESS TRANSFERS. Each operand transfer in the dual address mode will re-quire at least two and as many as four bus cycles in response to each operand transfer request.

Table 5-4 shows the number of bus cycles required to transfer each operand for the eight memory, device, and operand combinations.

Byte Operand

Word Operand

Table 5-4. Bus Cycles Per Operand Transfer.l.Dual Address

8-Bit Memory 16-Bit Memory

8-Bit 16-Bit 8-Bit 16-Bit

Device Device Device Device

2 X 2 2*

4 3 3 2

* If internal request generation is used, two operands will be trans-ferred per cycle.

For the combinations that require two or four bus cycles per operand, an equal number of cycles will access memory and the device; for the three bus cycle cases, two cycles will access which ever port is smaller and one cycle will access the larger port. The bus cycle sequence will always follow the pattern of: read the entire operand using as many bus cycles as are required and then write the entire operand, again using as many bus cycles as are required. Also, there will never be any 'dead time' between the bus cycles of a dual address operand transfer, so that S7 of the first read cycle will be followed immediately by SO of the next read or write cycle, etc.

The address register and transfer count register sequencing during a dual address transfer will follow the rules discussed previously for increment amounts except for the case discussed in the next paragraph. The point at which an address register is incremented depends on whether it is us-ed as the source or destination pointer. If usus-ed for the source pointer, it will be incrementus-ed after each operand part is successfully transferred to the internal holding register and if used for the destination pointer, it will be incremented after each operand part is successfully transferred from the internal holding register. Thus, the address registers will be incremented by one after each bus cycle required to transfer word operands to or from an 8-bit memory or device. The MTCR will be decremented by one when the last bus cycle of the operand transfer has been completed success-fully.

For most combinations of memory device, and operand size, the number of bus cycles run for each operand transfer count will be two, three, or four, according to Table 5-4, regardless of the operand request generation method used or transfer count value. One combination that is not consistent

the same manner as it would if the operand size were word; i.e., the MAR and DAR must be even and word reads and writes will be used to transfer two bytes per internal request. The MAR and DAR will be incremented by two (if programmed for increment) and the MTCR will be decremented by two after each transfer operation, except when the initial transfer count is odd, in which case the last transfer will be for a single byte.

Once the DDMA has started a dual address operand transfer, it must complete that transfer before releasing ownership of the bus or servicing requests for another channel of equal or higher priority, unless one of the bus cycles during the transfer is terminated with a relinquish and retry condition.

When any bus cycle is terminated with a halt, the DDMA will halt operation and release ownership of the bus immediately following the termination of that bus cycle. When the BEC encoding is returned to normal and bus ownership is returned to the DDMA, any operand transfer previously suspended must then be completed, regardless of pending requests for the other channel. The same rule applies to cycles terminated with retry or relinquish and retry; the same cycle that was ter-minated with the retry will be run again before the other channel can be serviced. If a bus cycle is terminated with a bus error, the channel operation will be terminated and any portion of the operand that was read but not yet written to the destination will be lost.

5.4.1.3 TRANSFER COUNT SYNCHRONIZATION. An important consideration in any system where two devices (the DDMA and a peripheral) are transferring a fixed number of data items is that both devices count the same number of operand transfers under all conditions. The DDMA facilitates this count synchronization with the DTC signal in two ways. First, DTC always indicates to a device that a bus cycle to transfer an operand or part of an operand has been successfully com-pleted so that the device may update its transfer pointer (for an internal FI FO for example). Second, if the device counts the number of assertions of DTC and knows how many device bus cycles are required to transfer each operand, it can properly decrement its transfer counter in step with the DDMA MTCR. A device should never use ACK by itself to clock pointer and counter registers if it is desired to support exceptional bus conditions. This is due to the fact that ACK will be asserted at the beginning of a bus cycle, but if a bus cycle is terminated with a bus error, retry, or relinquish and retry, DTC will not be asserted.

5.4.2 Effects of Channel Priority

When both channels of the DDMA are active, there exist:;> the possibility that operand transfers for both channels will be interleaved due to the priority scheme used to resolve simultaneous pending requests. The effects of channel priority on the operand transfer sequence during simultaneous channel operations is independent of the request generation method or transfer protocol used. In all cases, the following rules apply to the operand transfer order used.

1. Once a channel has started the transfer of an operand, the entire operand must be success-fully transferred or the channel operation aborted before the other channel may be serviced, regardless of priority relationships. The halt, retry, and relinquish and retry exceptional bus conditions will not affect the order in which operands are transferred, only the order of bus cycles during an operand transfer or the delay between successive bus cycles. For example, if the lower priority channel is being serviced and a bus cycle is terminated with a relinquish and retry, when the DDMA regains bus ownership, the lower priority operand transfer will be completed even if a higher priority request is pending. This is to preserve the contents of the internal data holding register.

2. If the two channels are at different priority levels, the lower priority channel will not be ser-viced as long as the higher priority channel has a request being serser-viced or pending.

3. If both channels are at the same priority level and have pending requests, the last channel serviced will be the last channel serviced again. For example, if both channels use internal maximum rate request generation and are active simultaneously, successive operand transfers will service alternate channels.