REGISTER DESCRIPTION
SECTION 4 BUS OPERATION
4.5 BUS ARBITRATION
-DDMA Owns Bus
REON
I
RRT, HLT RRT,HLT RRT,HLTDMA Mode NRM DMAMode
~
DMA Mode--+ No Active ~ Waiting For Waiting For
Cycle BEC Clear BEC Clear
I
RTY,BERj
To Retry~
NRMBER PTS
DMA Mode RRT
Bus Cycle
DTACK and NRM Active
DTACKandHLT
BEC Conditions:
NRM - Normal (No Exception)
Other Signals:
REO - ~ Channel Request
HLT - Halt PTS - Permission to Start
BER - Bus Error DTACK - Data Transfer Acknowledge
RTY - Retry
RRT - Relinquish and Retry RST - Reset
Figure 4-19. Bus Exception Control Flow Diagram
4.5 BUS ARBITRATION
Once the system processor has initialized and started a DDMA channel and an operand transfer re-quest has been made pending, either by an external device or the internal rere-quest generator, the DDMA will use the M68000 bus arbitration protocol to request bus mastership before entering the DMA mode of operation. The following paragraphs describe the arbitration protocol used by the DDMA and several special cases of operation relative to bus arbitration. Figure 4-20 sh~ws a func-tional timing diagram of a typical bus arbitration sequence.
S4 S5 S6 S7 SO S 1 S2 S3 S4 S5 S6 S7 S1 S2 S3 S4 S5 S6 S7 SO Sl S2 elK
BR I
BG
,
IT-
OWN~ BGACR
---~
____________________________
~f'---
---~---~,---AS _ _ _ _ oJ I
,~
_________
__'f'---'---,\~________
_J~---~- - - O t h " Bu, M"tec •
r
Fcoot Eod Oveme'd-+---OOMA CYde-+BOO' Eod Oveche,d--t
Ne" Bu, M"tec*The front end overhead will be one clock cycle less than shown if only one channel is active.
* *The back end overhead will be one clock cycle less than shown if a DMA cycle is terminated with halt or relinquish and retry.
Figure 4-20. Bus Arbitration Timing Diagram
4.5.1 Requesting and Receiving the Bus
When an active channel has an operand transfer request pending, the DDMA will request bus mastership by asserting the BR signal. An external bus arbiter (either a separate unit such as the MC68452 Bus Arbitration Module or the arbiter built into an M68000 processor) will then assert BG to indicate that bus mastership will belong to the DDMA as soon as the current bus master has
re-leased the bus. The DDMA then monitors the AS and BGACK signals to determine when it may assume mastership of the bus; these two signals must be negated to indicate that the previous bus cycle is complete and the previous bus master has released the bus. When this condition is met, the DDMA will assert OWN after a synchronization delay plus one-half clock cycle and then assert BGACK to indicate that it has taken control of the bus. One clock after BGACK is asserted, BR will be negated to allow the external arbiter to begin arbitration for the next bus master. Once all operand transfer requests have been serviced, the DDMA will release control of the bus by negating BGACK and will then negate OWN one-half clock cycle later. Note that OWN may be used to con-trol a bidirectional buffer for BGACK since it is asserted before and negated after BGACK is asserted and negated resp(3ctively.
4.5.2 Bus Overhead Time
In asynchronous bus systems such as those defined for the M68000 Family, a certain amount of time is used to synchronize incoming signals and is thus 'wasted' since no data transfer activity can take place during those periods. In many applications, the synchronization overhead time required to switch bus masters and channels within the DDMA must be known to predict system behavior.
The following paragraphs describe three types of overhead periods: those associated with the DDMA taking control of the bus, those in between successive operand transfers, and those that oc-cur when the DDMA is releasing control of the bus to another bus master. In all of these discus-sions, the system is assumed to consist of a single M68000 processor and a single DDMA using the same clock so that all arbitration delays are controlled by those two devices and can be predicted, as shown in Figure 4-20.
4.5.2.1 FRONT-END OVERHEAD. This is the delay that will occur from the time that the MPU ter-minates a bus cycle by negating AS (in S7 of the MPU cycle) to when the DDMA starts a bus cycle by placing function code and address information on the bus (in SO of the DMA cycle). It is assum-ed that BG is assertassum-ed and BGACK is negatassum-ed prior to the negation of AS by the MPU so that no ad-ditional synchronization delays are introduced by those signals. After one synchronization delay plus one-half clock cycle, the DDMA will assert OWN and one-half clock later assert BGACK to in-dicate that it is assuming bus mastership and begins to drive the function code and address lines.
When the DDMA asserts BGACK to assume control of the bus, it may also perform an internal channel arbitration to determine which channel will be serviced. This internal arbitration is required to be certain that the highest priority channel is serviced first, even if a lower priority channel issued a request first and started the bus arbitration sequence. If only one channel is active when the DDMA receives the bus, this arbitration is unnecessary and will not be performed. However, if both channels are active, then this arbitration will introduce one additional clock cycle of delay before the DDMA asserts AS. If the lower priority channel issued a request first and started the bus arbitration sequence, but the higher priority channel also has an operand transfer request pen-ding by the time BGACK is asserted, then the function code and address/ data lines will first be driven with addresses from the lower priority channel for one clock cycle and then change to the ad-dresses from the higher priority channel. If the higher priority channel had issued the original
remain stable for one extra clock before AS is asserted. Neither of these cases will cause an er-roneous address decode since AS will not be asserted until the function code and address pins are stable.
Taking into consideration the above factors of internal arbitration and synchronization delays, the best case front-end overhead time istwo clock cycles if AS is sampled as negated by the DDMA at the end of S7 in the M PU cycle and only one channel is active. The worst case front-end overhead is four clock cycles if AS is not negated until after the rising edge of S7 in the M PU cycle and both channels are active.
4.5.2.2 INTER-CYCLE OVERHEAD. This is the overhead delay that will occur between successive DMA bus cycles for either or both of the channels while the DDMA maintains ownership of the bus.
Such a delay will occur if a channel with priority equal to or higher than the priority of the channel being serviced has an operand transfer request pending at the completion of an operand transfer, or when a new cycle steal request is asserted for the current chann~1.
The inter-cycle overhead time is illustrated in Figure 4-21 where the three cases of zero, one, and two clock cycles are shown. If a channel switch is not necessary and the current channel has further cycle steal transfer requests asserted by E1 (where E1 is the rising clock edge one clock before the edge on which DTC is asserted), then the inter-cycle overhead time is zero. The second case of one clock overhead will occur when a channel switch request is asserted by E1 in the current bus cycle, or if a cycle steal request for the current channel is not asserted until E2 (where E2 is the rising clock edge on which DTC is asserted). The worst case will occur if a channel switch request is not asserted until after E1, but before E2. If no requests are asserted for either channel when the DDMA reaches E2, it will release ownership of the bus and a minimum of the back-end and front-end overhead times will occur before another operand transfer will be able to star1 (plus any bus cycle time used by another bus master before the DDMA regains control of the bus). For the one and two clock overhead cases, the DDMA may begin to drive the function code and address pins with the values for the next operand of the current channel for one clock cycle before changing to the values for the higher priority channel. This will not cause invalid address decoding since AS will not be asserted until the function code and address pins are stable.
One other case of inter-cycle overhead time is related to the reload mode of operation and is very similar to the overhead time for channel switches. A more detailed description of the delays associated with this type of operation is given in 5.5 SPECIAL CHANNEL OPERATIONS.
4.5.2.3 BACK-END OVERHEAD. This overhead time is the delay between when the DDMA has completed all pending operand transfers and releases the bus, plus the synchronization of BGACK negated by the MPU. When the DDMA has completed the last pending bus cycle in S7 for a DMA read or S9 for a DMA write, it will negate BGACK after a one clock cycle delay. The MPU will then wait one synchronization delay plus one-half clock cycle before SO of the next MPU cycle. Given these restraints, the best case back-end overhead time is three clock cycles and the worst case is four clock cycles.
f"
N -....J
SO S1 ClK
SA BG B GACK ---",
A1-A7 -:---C
AS
S2
,
Channel Switch Detected
E2 S5 \ S6 S7
I
,
DTC ~r---~
I.
ChanneIO---~~-Channel Switch Detected
SO S1 S2 S7
No Switch, New Request
Detected
SO S1 S2
Channel 0 In this example, CHO is using burst requests and is at priority 1, CHl is using cycle steal requests and is at priority O.
Figure 4-21. Inter-Cycle Overhead Timing Diagram
S7 SO S1 S2
I
• ,
~
'---'
.1 ..
o Clocks I
No Requests Detected
S7
,--.
r
~
Channel 0
-I
,..-4.5.2.4 OVERHEAD DUE TO BEC OPERATION. When a BEC encoding of bus error, retry, or undefined is asserted during a bus cycle, the DDMA will introduce delays after it terminates the bus cycle while it performs internal operations before starting the next bus cycle or releasing ownership of the bus. If a bus cycle is terminated with a halt or relinquish and retry BEC encoding, then the back-end overhead time will also be affected.
If a bus cycle is terminated with a bus error, there will be a five clock minimum delay before the DDMA starts the next bus cycle or releases ownership of the bus. If a bus cycle is terminated with a retry, there will be a three clock minimum delay before the DDMA starts the retry operation. If a bus cycle is terminated with an undefined code, there will be a two clock minimum delay before the DDMA continues operation. All of these minimum delay times assume that the BEC encoding is returned to normal as soon as AS is negated and that encoding is valid for the required setup time before the next rising edge of the clock (the end of S7 for read cycles or S9 for write cycles).
If a bus cycle is terminated with a relinquish and retry or a DT ACKI halt, the back-end overhead time will be one clock cycle less than for normal operation.