E 2
RR 2
RRE 4
RS 4
RX 4
S 4
SI 4
5S 6
SSE 6
When you code machine instructions, you use symbolic formats that correspond to the actual machine language formats. Within each basic format, you can also code variations of the symbolic representation, divided into groups according to the basic formats illustrated below.
The assembler converts only the operation code-and the operand entries of the assembler language statement into object code.
The assembler assigns to the symbol you code as a name entry the
v~lue of the address of the leftmost byte of the assembled
instruction. When you use this same symbol in the operand of an assembler language statement, the assembler uses this address value in converting the symbolic operand into its object code form. The length attribute assigned to the symbol depends on the basic machine language format of the instruction in which the symbol appears as a name entry.
A remarks entry is not converted into object code.
An example of a typical assembler language statement follows:
LABEL L 4,256(5,10) LOAD INTO REG4 where
LABEL is the name entry.
L is the operation code (converted to 58).
-4 is the register operand (copied).
256(5,10) are the storage operand entries (converted to 5AIOO).
LOAD INTO REG4 (remarks) is not converted into object code.
The object code of the assembled instruction, in hexadecimal, is:
5845AI00 (4 bytes in RX format) SYMBOLIC OPERATION CODES
You must specify an operation code for each machine instruction statement. The symbolic operation code indicates the type of operation to be performed; for example, A indicates the addition operation. See Appendix D, "Macro Language Summary" for a
complete list of symbolic operation codes; see the appropriate 70 Assembler H Version 2 Application Programming: Language Reference
o
o
0
Extended Code Meaning Format (Symbolic) MachineUsed After Compare Instructions
BH D2(X2,B2) Branch on High RX BC 2,D2(X2,B2)
Used After Test Under Mask Instructions
BO D2(X2,B2)
}
Branch if Ones RX BC I,D2(X2,B2)D2=displacement,X2=index register,B2=base register,R2=register containing branch address
Figure 17. Extended Mnemonic Codes
0
Chapter 4. Machine Instruction Statements 71
OPERAND ENTRIES
principles of operation for the formats of the corresponding machine instructions.
The general format of the machine instruction operation code is:
VERB [MODIFIER] [DATA TYPE] [MACHINE FORMAT]
The verb must always be present. It usually consists of one or
tw~ characters and specifies the operation to be performed. The verb is underscored in the following examples:
A
3,AREA orMVC TO, FROM where
A
indicates an add operation, and~~ indicates a move operation.
The other items in the operation code are not always present.
They include the following (underscores are used to indicate modifiers, data types, and machine formats in the examples below):
• Modifier, which further defines the. operation
Ai 3,AREA where lindicates a logical operation
• Type qualifier, which indicates the type of data used by the instruction in its operation
CVIl 3,BIHAREA where B indicates binary data
MV~ TO, FROM where C indicates character data Ag 2,FlT5HRT where E indicates normalized short
floating-point data
AJ1 2,FlTlOHG where D indicates normalized long floating-point data
• Format qualifier, R or I, which indicates that an RR or SI machine instruction format is assembled
AD& 2,4 where R indicates an RR instruction MVI FIElD,X'Al' where I indicates an 51 instruction
You must specify one or more operands in each machine
instruction statement to provide the data or the location of the data upon which the machine operation is to be performed. The operand entries consist of one or more fields or subfields, depending on the format of the instruction being coded. They can specify a register, an address, a length, and immediate data.
You can code an operand entry either with symbols or with self-defining terms. You can omit length fields or subfields, which the assembler will compute for you from the other operand entries.
72 Assembler H Version 2 Application Programming: language Reference
o
(-'"
~=f'
o
REGISTERS
o
o
The rules for coding operand entries are:
1. A comma must separate operands.
2. Parentheses must enclose subfields.
3. A comma must separate subfields enclosed in parentheses.
If a subfield is omitted because it is implicit in a symbolic address, the parentheses that would have enclosed the subfield must be omitted.
If two subfields are enclosed in parentheses and separated by commas, the following"applies:
• If both subfields are omitted because they are implicit in a symbolic entry, the separating comma and the parentheses that would have been needed must also be omitted.
• If the first subfield is omitted, the comma that separates it from the second subfield must be written, as well as the enclosing parentheses.
• If the second subfield is omitted, the comma that separates it from the first subfield must be omittedi however, the enclosing parentheses must be written.
Note:
Blanks must not appear within the operand field, except as part of a character self-defining term, or in thespecification of a character literal.
You can specify a register in an operand for Use as an
arithmetic accumulator, a base register, an index register, and as a general depository for data to which you wish to refer repeatedly.
You must be careful when specifying a register whose contents have been affected by the execution of another machine
instruction, the control program, or an IBM-supplied system macro instruction.
For some machine instructions, you are limited in which registers you can specify in an operand.
The expressions used to specify registers must have absolute values; in general, registers 0 through 15 can be specified for machine instructions. However, the following restrictions on register usage apply:
1. The floating-point registers (0, 2, 4, or 6) must be specified for floating-point instructions.
2. The even-numbered registers (0, 2, 4, 6, 8, 10, 12, 14) must be specified for the following groups of instructions:
a. The double-shift instructions
b. The fullword multiply and divide instructions
c. The move long and compare logical long instructions 3. The floating-point registers 0 and 4 must be specified for
the instructions that use extended floating-point data: AXR, SXR, LRDR, MXR, MXDR, MXD, and DXR.
Note:
The assembler checks the registers specified in the instruction statements of the above groups. If the specified register does not comply with the stated restrictions, the assembler issues a diagnostic message and does not assemble the instruction.Chapter 4. Machine Instruction Statements 73