Arithmetic Instructions

Arithmetic instructions perform arithmetic operations on values in registers.

(Floating-point arithmetic instructions are described in Section 4.3.) Table 3-4 lists the mnemonics and operands for instructions that perform arithmetic operations. The table is segmented into groups of instructions.

The operands specified within a particular segment apply to all of the instructions contained in that segment.

Clear

Absolute Value Longword Absolute Value Quadword

Negate Longword (without overflow) Negate Longword (with overflow) Negate Quadword (without overflow) Negate Quadword (with overflow) Sign-Extension Longword

Add Longword (without overflow) Add Longword (with overflow) Add Quadword (without overflow) Add Quadword (with overflow) Scaled Longword Add by 4 Scaled Quadword Add by 4 Scaled Longword Add by 8 Scaled Quadword Add by 8

Multiply Longword (without overflow) Multiply Longword (with overflow) Multiply Quadword (without overflow) Multiply Quadword (with overflow) Subtract Longword (without overflow) Subtract Longword (with overflow) Subtract Quadword (without overflow) Subtract Quadword (with overflow) Scaled Longword Subtract by 4 Scaled Quadword Subtract by 4 Scaled Longword Subtract by 8 Scaled Quadword Subtract by 8 Unsigned Quadword Multiply High Divide Longword s_regJ, vaCimmed, d_reg d_regls_regJ, vaCimmed

Table 3-5 describes the operations performed by arithmetic instructions.

Table 3-5: Arithmetic Instruction Descriptions

Instruction Clear (clr)

Descri ption

Sets the contents of the destination register to zero.

Absolute Value Longword (absl)

Computes the absolute value of the contents of the source register and puts the result in the destination register. If the value in the source register is -2147483648, an overflow exception is signaled.

Absolute Value Quadword (absq)

Computes the absolute value of the contents of the source register and puts the result in the destination register. If the value in the source register is -9223372036854775808, an overflow exception is signaled.

Negate Longword (without overflow) (negl)

Negates the integer contents of the four least significant bytes in the source register and puts the result in the destination register. An

overflow occurs if the value in the source register is -2147483648, but the overflow exception is not signaled.

Negate Longword (with overflow) (negl v)

Negates the integer contents of the four least significant bytes in the source register and puts the result in the destination register. If the value in the source register is -2147483648, an overflow exception is signaled.

Negate Quadword (without overflow) (negq)

Negates the integer contents of the source register and puts the result in the destination register. An overflow occurs if the value in the source register is -2147483648, but the overflow exception is not signaled.

Negate Quadword (with overflow) (negqv)

Negates the integer contents of the source register and puts the result in the destination register. If the value in the source register is -9223372036854775808, an overflow exception is signaled.

Sign-Extension Longword (sextl)

Moves the four least significant bytes of the source register into the four least significant bytes of the destination register. Because the moved longword is a signed value, its sign bit is replicated to fill the other bytes in the destination register.

Add Longword (without overflow) (addl)

Computes the sum of two signed 32-bit values.

This instruction adds the contents of s_reg 1 to the contents of s_reg2 or the immediate value and then puts the result in the destination register. Overflow exceptions never occur.

Add Longword (with overflow) (addlv)

Computes the sum of two signed 32-bit values.

This instruction adds the contents of s reg 1 to the contents of s reg2 or the immedIate value and then puts theresult in the destination register. If the result cannot be represented as a signed 32-bit number, an overflow exception is signaled.

Add Quadword (without overflow) (addq)

Computes the sum of two signed 64-bit values.

This instruction adds the contents of s reg 1 to the contents of s reg2 or the immedIate value and then puts theresult in the destination register. Overflow exceptions never occur.

Add Quadword (with overflow) (addqv)

Computes the sum of two signed 64-bit values.

This instruction adds the contents of s reg 1 to the contents of s reg2 or the immedIate value and then puts theresult in the destination register. If the result cannot be represented as a signed 64-bit number, an overflow exception is signaled.

Scaled Longword Add by 4 (s4addl)

Computes the sum of two signed 32-bit values.

This instruction scales (multiplies) the contents of s reg 1 by four and then adds the contents of s reg2 or the immediate value. The result is

Table 3-5: (continued)

Instruction Description

Scaled Quadword Add by 4 (s 4 addq)

Computes the sum of two signed 64-bit values.

This instruction scales (multiplies) the contents of s reg 1 by four and then adds the contents of s reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.

Scaled Longword Add by 8 (s8addl)

Computes the sum of two signed 32-bit values.

This instruction scales (multiplies) the contents of s reg 1 by eight and then adds the contents of s -reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.

Scaled Quadword Add by 8 (s 8 addq)

Computes the sum of two signed 64-bit values.

This instruction scales (multiplies) the contents of s reg 1 by eight and then adds the contents of s -reg2 or the immediate value. The result is stored in the destination register. Overflow exceptions never occur.

Multiply Longword (without overflow) (mull)

Computes the product of two signed 32-bit values. This instruction puts the 32-bit product of s reg 1 and s reg2 or the immediate value in the destination register. Overflows are not reported.

Multiply Longword (with overflow) (mull v)

Computes the product of two signed 32-bit values. This instruction puts the 32-bit product of s regl and s reg2 or the immediate value in the destination register. If an overflow occurs, an overflow exception is signaled.

Multiply Quadword (without overflow) (mulq)

Computes the product of two signed 64-bit values. This instruction puts the 64-bit product of s reg 1 and s reg2 or the immediate value in the destination register. Overflow is not reported.

Multiply Quadword (with overflow) (mulqv)

Computes the product of two signed 64-bit values. This instruction puts the 64-bit product of s reg 1 and s reg2 or the immediate value in the destination register. If an overflow occurs, an overflow exception is signaled.

Subtract Longword (without overflow) (subl)

Computes the difference of two signed 32-bit values. This instruction subtracts either the contents of s reg2 or an immediate value from the contents

Of

s reg 1 and then puts the result in the destination register. Overflow exceptions never happen.

Subtract Longword (with overflow) (subl v)

Computes the difference of two signed 32-bit values. This instruction subtracts either the contents of s reg2 or an immediate value from the contents

Of

s reg 1 and then puts the result in the destination register. If the true result's sign differs from the destination register's sign, an overflow exception is signaled.

Subtract Quadword (without overflow) (subq)

Computes the difference of two signed 64-bit values. This instruction subtracts the contents of s reg2 or an immediate value from the contents of s reg 1 and then puts the result in the destination register. Overflow exceptions never occur.

Subtract Quadword (with overflow) (subqv)

Computes the difference of two signed 64-bit values. This instruction subtracts the contents of s reg2 or an immediate value from the contents of s reg 1 and then puts the result in the destination register. If the true result's sign differs from the destination register's sign, an overflow exception is signaled.

Table 3-5: (continued)

Instruction Description

Scaled Longword Subtract by 4 (s4subl)

Computes the difference of two signed 32-bit values. This instruction subtracts the contents of s reg2 or the immediate value from the scaled

(bY

4) contents of s reg 1. The result is stored in the destination register. Overflow exceptions never occur.

Scaled Quadword Subtract by 4 (s4subq)

Computes the difference of two signed 64-bit values. This instruction subtracts the contents of s reg2 or the immediate value from the scaled (by 4) contents of s reg 1. The result is stored in the destination register. Overflow exceptions never occur.

Scaled Longword Subtract by 8 (s8subl)

Computes the difference of two signed 32-bit values. This instruction subtracts the contents of s reg2 or the immediate value from the scaled

(bY

8) contents of s reg 1. The result is stored in the destination register. Overflow exceptions never occur.

Scaled Quadword Subtract by 8 (s 8subq)

Computes the difference of two signed 64-bit values. This instruction subtracts the contents of s reg2 or the immediate value from the scaled

(bY

8) contents of s reg 1. The result is stored in the destination register. Overflow exceptions never occur.

Unsigned Quadword Multiply High (umulh)

Computes the product of two unsigned 64-bit values. This instruction multiplies the contents of s reg 1 by the contents of s reg2 or the immediate value and then putsthe high-order 64 bits of the 128-bit product in the destination register.

Divide Longword (divl) Computes the quotient of two signed 32-bit values. This instruction divides the contents of s regl by the contents of s reg2 or the immediate value and then puts the quotient in the destination register.

The di vI instruction rounds toward zero. If the divisor is zero, an error is signaled and a call pal PAL gentrap instruction may be issued-: Overflow

is

signaled when dividing -2147483648 by -1. A call pal

PAL gentrap instruction may be issued for either divide-by-zero or overflow.

Divide Longword Unsigned (divlu)

Divide Quadword (di vq)

Computes the quotient of two unsigned 32-bit values. This instruction divides the contents of s reg 1 by the contents of s reg2 or the immediate value and then putsthe quotient in the destination register.

If the divisor is zero, an exception is signaled and a call pal PAL gentrap instruction may be issued. Overflow exceptions never occur.

(The assembler uses temporary registers AT, t9, t 10, t 11, and t 12 for this instruction.) Computes the quotient of two signed 64-bit values. This instruction divides the contents of s regl by the contents of s reg2 or the immediate value and then putsthe quotient in the destination register.

The di vq instruction rounds toward zero. If the divisor is zero, an error is signaled and a

call pal PAL gentrap instruction may be issued-: Overflow IS signaled when dividing -9223372036854775808 by -1. A call pal PAL gent rap instruction may be issued for either divide-by-zero or overflow. (The

assembler uses temporary registers AT, t9, tl0, t 11, and t 12 for this instruction.)

Table 3-5: (continued)

Instruction Description

Divide Quadword Unsigned (di vqu)

Longword Remainder (reml)

Computes the quotient of two unsigned 64-bit values. This instruction divides the contents of s regl by the contents of s reg2 or the immediate value and then putsthe quotient in the destination register.

If the divisor is zero, an exception is signaled and a call pal PAL gentrap instruction may be issued. Overflow exceptions never occur.

(The assembler uses temporary registers AT, t9, tID, tIl, and t 12 for this instruction.) Computes the remainder of the division of two signed 32-bit values. The remainder

reml(i,j) is defined as i-(j*divl(i,j»

where j != O. This instruction divides the contents of s reg 1 by the contents of s reg2 or by the immediate value and then puts the remainder in the destination register.

The reml instruction rounds toward zero. For example, divl (5, -3) =-1, and reml (5,-3 )=2.

For divide-by-zero, an error is signaled and a call pal PAL gentrap instruction may be issued~ (The assembler uses temporary registers AT, t9, tID, tIl, and t12 for this instruction.) Longword Remainder Unsigned (remlu)

Computes the remainder of the division of two unsigned 32-bit values. The remainder remlu ( i, j ) is defined as

i-(j*divlu(i,j» wherej !=O. This instruction divides the contents of s reg 1 by the contents of s reg2 or the immediate value and then puts the remainder in the destination register.

For divide-by-zero, an error is signaled and a call pal PAL gentrap instruction may be issued~ (The assembler uses temporary registers AT, t9, tID, tIl, and t12 for this instruction.)

Quadword Remainder (remq) Computes the remainder of the division of two signed 64-bit values. The remainder

remq ( i, j ) is defined as i- ( j *di vq ( i, j ) ) where j != O. This instruction divides the contents of s reg 1 by the contents of s reg2 or the immediate value and then puts the -remainder in the destination register.

The remq instruction rounds toward zero. For example, divq(S,-3)=-I, and remq(S,-3 )=2.

For divide-by-zero, an error is signaled and a call pal PAL gentrap instruction may be issued~ (The assembler uses temporary registers AT, t9, tID, tIl, and tl2 for this instruction.) Quadword Remainder Unsigned (remqu)

Computes the remainder of the division of two unsigned 64-bit values. The remainder remqu ( i , j ) is defined as

i-( j *di vqu ( i, j ) ) where j != O. This instruction divides the contents of s reg 1 by the contents of s reg2 or the immediate value and then puts the remainder in the destination register.

For divide-by-zero, an error is signaled and a call pal PAL gentrap instruction may be issued~ (The assembler uses temporary registers AT, t9, tID, tIl, and tl2 for this instruction.)

Dans le document DEC aSF/1 (Page 44-53)