• Aucun résultat trouvé

CURRENT PATH IN AMORPHOUS-SILICON FIELD EFFECT TRANSISTORS

N/A
N/A
Protected

Academic year: 2021

Partager "CURRENT PATH IN AMORPHOUS-SILICON FIELD EFFECT TRANSISTORS"

Copied!
5
0
0

Texte intégral

(1)

HAL Id: jpa-00220728

https://hal.archives-ouvertes.fr/jpa-00220728

Submitted on 1 Jan 1981

HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci- entific research documents, whether they are pub- lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers.

L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

CURRENT PATH IN AMORPHOUS-SILICON FIELD EFFECT TRANSISTORS

M. Matsumura, S. Kuno, Y. Uchida

To cite this version:

M. Matsumura, S. Kuno, Y. Uchida. CURRENT PATH IN AMORPHOUS-SILICON FIELD EFFECT TRANSISTORS. Journal de Physique Colloques, 1981, 42 (C4), pp.C4-519-C4-522.

�10.1051/jphyscol:19814111�. �jpa-00220728�

(2)

CURRENT PATH I N AMORPHOUS-SILI'CON F I E L D EFFECT TRANSISTORS

M. Matsumura, S.I. Kuno and Y. Uchida

Department of Physical EZectronics, Tokyo I n s t i t u t e o f TechnoZogy, Oh-okayama, Meguro-ku, Tokyo 152, Japan

Abstract.- On-resistance of amorphous-silicon field effect transistors with staggered electrodes was investigated. It was found that dependences of the on-resistance on geometrical parameters were classified into two groups. The origin was attributed to the residual resistance between the nt el-ectrode and the channel which was formed at the silicon-silicon dioxide interface. The resistance was analyzed by taking space charge effect into account, and we found that it changes in accordance with sample preparation conditions. It is pointed out that caution should be taken not only in transistor design but also in mobility evaluation and gap-state-density evaluation.

Introduction.- One of the important parameters of amorphous-silicon field effect transistors(a-Si FETs) (1) is the on-off current ratio. Recently, we obtained a high on-off current ratio (more than 10 8 ) by using transistors with a staggered electrode structure (2). However, from a simple geometrical consideration, the maximum obtain- able value was estimated to be 104. In this paper, we would like to report that 1) this discrepancy arised from a drastic decrease of the residual resistance of the active n- a-Si caused by the space charge effect, 2) this value changes by sample preparation conditions because it varies with localized state density, thickness and Fermi potential, and 3) the current path in the a-Si FETs changes from sample to sample according to the residual resistance.

Experimental Results.- Figure 1 shows a cross-sectional view of our FETs. The FET. had

-

t

nf-n -n structure with staggered electrodes and was prepared on a crystal silicon substrate, with various n electrode spacing t L and n- island length L'. The gate oxide thickness and channel width W

were fixed at 0.5pm and 200um.

respectively. The films were

4

L'

>

deposited by the hot cathode arc

L

discharge decomposition method (3). 5---)

I

Uniformity of the FET characteristics

was excellent (on-current and off-

n+ n+

current variations were less than 50%) but reproducibility was not good.

i : :--I-:L

I

i

:

path+,!

.-L-->--:

n- ---l $R! ,

Figure 2 shows typical drain current ID vs. gate voltage VG

characteristics. The maximum current

Tox Si02

was 130uA and the minimum current was

about IPA. Thus the on-off current

G

ratio y is more than 10 8

.

Fig.1. Cross-sectional view of FET with Under low drain voltage VD and staggered electrode.

Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jphyscol:19814111

(3)

JOURNAL DE PHYSIQUE

high

V

G conditions, a group of I'ETs on a substrate showed ID-VD characteristics as shown in Fig.3. The on-resistance --L, Q

V

R

on =dVD/dID

E -5

was not given by L and was proportional m to Lt. Thus the current is considered to 0 flow along the Si-Sio2 interface from

-J-6

one edge of the n- island to the other

- 7

edge of the n- island as shown by a solid line in Fig.1. However, a group of FETs on another substrate showed I -V

D D

- 8

characteristics as shown in Fig.4. The

on-resistance was proportional to L and

-9

did not depend on L'. Thus it can be

considered that the current first

crosses the n- layer downwards, then flows

-10

along the Si-Si02 interface and again

crosses the n- layer upwards, as shown by

-11

dotted lines in Fig.1.

The different path that the current took was caused by the resistance R between the n electrode and the channel t formed at the Si-Si02 interface. When R

is high, the FETs show the former

0

characteristics because the voltage drop

VG ( V )

f Fig.2. Typical semilogarithmic

between the upper n electrode and the dependence of ID on V lower channel is high. And when R is V was fixed at 40V. G'

low, the FET show the latter D

Fig.3. I -V characteristics of the FETs with the current path shown by s8li8 line in Fig.1.

(4)

T h e o r e t i c a l Results,- I n case where t h e c u r r e n t flows a l o n g t h e d o t t e d l i n e s i n Fig.1 i f we n e g l e c t channel r e s i s t a n c e , Ron equals t o 2R and i s given by

where p i s t h e s p e c i f i c r e s i s t a n c e of t h e n- l a y e r . d t h e t h i c k n e s s of t h e a c t i v e n- l a y e r . Since t h e o f f - r e s i s t a n c e Roff i s expressed by

y becomes a s

R (L-L1 )L

y= off/Ron=

b2

I n s e r t i n g t y p i c a l v a l u e s i n t o L,LV and d . y was c a l c u l a t e d t o be 104, which i s much l e s s than t h e e x p e r i m e n t a l l y o b t a i n e d value. This discrepancy can be explained by t h e f a c t t h a t R i s a space charge l i m i t e d r e s i s t a n c e s i n c e a high r e s i s t i v e n- l a y e r was sandwitched between t h e nt e l e c t r o d e and t h e channel.

F i g u r e 5 shows t h e c a l c u l a t e d p o t e n t i a l and c a r r i e l : d e n s i t y d i s t r i b u t i o n s i n

t t

t h e n -n--n a-Si diodes. The l o c a l i z e d s t a t e d e n s i t y d i s b r i b u t i o n assumed i s shown i n Fig.6. When t h e c u r r e n t f l o w s , a l a r g e number 0:: excess e l e c t r o n s appear i n t h e n- l a y e r , r e s u I t i n g i n a d r a s t i c d e c r e a s e of i t s r e s i s t a n c e . ~ o w e v e r , d i s t a n t from t h e nt cathode, excess e l e c t r o n d e n s i t y d e c r e a s e s and r e s i s t i v i t y approaches i t s

e q u i l i b l i u m value. Thus t h e space charge l i m i t e d r e s i s t a n c e can be observed o n l y i n t h e case of extremely narrow n- l a y e r and can n o t be observed i n conventional FE measurements. When t h e n- l a y e r i s 0.5urn and t h e c u r r e n t d e n s i t y i s l ~ / c m ~ , which a r e

(5)

JOURNAL DE PHYSIQUE

V I L J

Fig.5. C a r r i e r and p o t e n t i a l d i s t r i b u t i o n s i n

Fif.6. Localized s t a t e d e n s i t y d i s t r i b u t i o n assumed i n a n a l y s i s .

nf -n--nt a-Si diodes.

t y p i c a l v a l u e s i n a - S i FETs, t h e v o l t a g e drop a c r o s s t h e n- l a y e r was c a l c u l a t e d t o be about &V, which i s

4

o r d e r s i n magnxtude l e s s t h a n t h e v a l u e c a l c u l a t e d from s p e c i f i c r e s i s t a n c e . Thus t h e high c u r r e n t r a t i o o b t a i n e d e x p e r i m e n t a l l y can be explained by t h e d e c r e a s e of R

.

S i n c e R changes w i t h l o c a l i z e d s t a t e d e n s i t y d i s t r i b u t i o n and n- t h i c k n e s s and s i n c e i t i s c o m p a r a b l e t o t h e d r a i n v o l t a g e of t h e a-Si FETs, t h e c u r r e n t p a t h changes w i t h sample p r e p a r a t i o n c o n d i t i o n s .

It i s important t o express t h i s space charge e f f e c t a n a l y t i c a l l y . When we assume t h e l o c a l i z e d s t a t e d e n s i t y n e a r Fermi l e v e l t o t a k e t h e form nToexp(E;/a) and when t h e t h i c k n e s s d of t h e n- l a y e r i s much l e s s than t h e c h a r a c t e r i s t i c t h i c k n e s s do d e f i n e d by

ao=cap0J/ (qnTo(a+kT) )

.

Ron becomes

Ron=Rono ( ~ f k T ) (d/do) a / ( a t k T ) / ( 2 a + k ~ )

,

where J i s t h e c u r r e n t d e n s i t y and Rono t h e r e s i s t a n c e when t h e s p e c i f i c r e s i s t a n c e i s i t s e q u i l i b l i u m value.

Conclusion.- The importance of r e s i d u a l r e s i s t a n c e i n a-Si FETs was p o i n t e d o u t . Lack of r e p r o d u c i b i l i t y i s p a r t l y caused by t h i s r e s i s t a n c e . ~ n d s i n c e t h e e f f e c t i v e channel l e n g t h changes with t h e r e s i s t a n c e , c a r e f u l examination of t h i s r e s i s t a n c e i s necessary f o r evaluation of m o b i l i t y and l o c a l i z e d s t a t e d e n s i t y by FE method.

To e l i m i n a t e t h i s r e s i s t a n c e , coplanar e l e c t r o d e s t r u c t u r e must be a p p l i e d . References.

~)P.G. LeComber, W.E. Spear and A . Ghaith, Elect. ~ e t t . , s , 1 7 9 ( 1 9 7 9 ) . 2)H. Nayama and M. Matsumura, ~ ~ ~ , % , 7 5 4 ( 1 9 8 0 )

3)M. Matsumura and Y. Uchida, t o be presented a t t h i s conference.

Références

Documents relatifs

First, modulation of the nanowire conductance is measured as function of a back gate voltage (fig.3) ap- plied on the Si-substrate forcing charge accumulation at the

Here we work with long channels, longer than the optical phonon scattering length, to realize velocity saturation transistors with large voltage gain; contact gating is used instead

Then, the screw dislocation induced spiral growth turns to kinetic roughening and the threading pits are visible no more on the top of the mounds (the final GaN thickness was of

Here we work with long channels, longer than the optical phonon scattering length, to realize velocity saturation transistors with large voltage gain; contact gating is used instead

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around.. Youssouf Guerfi,

Since urea detection was shown in dialysate solutions, the urea-EnFET/pH-ReFET microsensor was finally tested for the urea on-line monitoring in dialysis conditions, using an

Abstract— The aim of our research project is to achieve a potentiometric multi-sensor platform, consisting of ion sensitive field effect transistors ISFET and

To assess the potential of our NSs as effective building materials in high performance flexible electronics, we fabricate organic (parylene C) / inorganic (ZnO NS) hybrid